mc9s08dz32amlfr Freescale Semiconductor, Inc, mc9s08dz32amlfr Datasheet - Page 149
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mc9s08dz32amlfr
Manufacturer Part Number
mc9s08dz32amlfr
Description
Hcs08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC9S08DZ32AMLFR.pdf
(458 pages)
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7.3.6.5
This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus a 16-bit offset
included in the instruction as the address of the operand needed to complete the instruction.
7.3.6.6
This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus an unsigned 8-bit
offset included in the instruction as the address of the operand needed to complete the instruction.
7.3.6.7
This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus a 16-bit offset
included in the instruction as the address of the operand needed to complete the instruction.
7.4
The CPU performs a few special operations that are similar to instructions but do not have opcodes like
other CPU instructions. In addition, a few instructions such as STOP and WAIT directly affect other MCU
circuitry. This section provides additional information about these operations.
7.4.1
Reset can be caused by a power-on-reset (POR) event, internal conditions such as the COP (computer
operating properly) watchdog, or by assertion of an external active-low reset pin. When a reset event
occurs, the CPU immediately stops whatever it is doing (the MCU does not wait for an instruction
boundary before responding to a reset event). For a more detailed discussion about how the MCU
recognizes resets and determines the source, refer to the
chapter.
The reset event is considered concluded when the sequence to determine whether the reset came from an
internal source is done and when the reset pin is no longer asserted. At the conclusion of a reset event, the
CPU performs a 6-cycle sequence to fetch the reset vector from 0xFFFE and 0xFFFF and to fill the
instruction queue in preparation for execution of the first program instruction.
7.4.2
When an interrupt is requested, the CPU completes the current instruction before responding to the
interrupt. At this point, the program counter is pointing at the start of the next instruction, which is where
the CPU should return after servicing the interrupt. The CPU responds to an interrupt by performing the
same sequence of operations as for a software interrupt (SWI) instruction, except the address used for the
vector fetch is determined by the highest priority interrupt that is pending when the interrupt sequence
started.
The CPU sequence for an interrupt is:
Freescale Semiconductor
1. Store the contents of PCL, PCH, X, A, and CCR on the stack, in that order.
2. Set the I bit in the CCR.
Special Operations
Reset Sequence
Interrupt Sequence
Indexed, 16-Bit Offset (IX2)
SP-Relative, 8-Bit Offset (SP1)
SP-Relative, 16-Bit Offset (SP2)
MC9S08DZ128 Series Data Sheet, Rev. 1
Resets, Interrupts, and System Configuration
Chapter 7 Central Processor Unit (S08CPUV5)
149
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