mc9s08dz32amlfr Freescale Semiconductor, Inc, mc9s08dz32amlfr Datasheet - Page 170

• Manufacturer Part Number: mc9s08dz32amlfr
• Description: Hcs08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 8 Multi-Purpose Clock Generator (S08MCGV2)
8.3
8.3.1
170
IREFSTEN
IRCLKEN
IREFS
CLKS
Field
RDIV
7:6
5:3
2
1
0
Reset:
Register Definition
W
R
MCG Control Register 1 (MCGC1)
Clock Source Select — Selects the system clock source.
00
01
10
11
External Reference Divider — Selects the amount to divide down the external reference clock. If the FLL is
selected, the resulting frequency must be in the range 31.25 kHz to 39.0625 kHz. If the PLL is selected, the
resulting frequency must be in the range 1 MHz to 2 MHz. See
Internal Reference Select — Selects the reference clock source.
1 Internal reference clock selected
0 External reference clock selected
Internal Reference Clock Enable — Enables the internal reference clock for use as MCGIRCLK.
1 MCGIRCLK active
0 MCGIRCLK inactive
Internal Reference Stop Enable — Controls whether or not the internal reference clock remains enabled when
the MCG enters stop mode.
1 Internal reference clock stays enabled in stop if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI mode before
0 Internal reference clock is disabled in stop
entering stop
Encoding 0 — Output of FLL or PLL is selected.
Encoding 1 — Internal reference clock is selected.
Encoding 2 — External reference clock is selected.
Encoding 3 — Reserved, defaults to 00.
7
0
CLKS
Table 8-1. MCG Control Register 1 Field Descriptions
0
6
Figure 8-3. MCG Control Register 1 (MCGC1)
MC9S08DZ128 Series Data Sheet, Rev. 1
0
5
RDIV
0
4
Description
0
3
Table 8-2
IREFS
and
1
2
Table 8-3
IRCLKEN
Freescale Semiconductor
for the divide-by factors.
0
1
IREFSTEN
0
0