mc9s08dz32amlfr Freescale Semiconductor, Inc, mc9s08dz32amlfr Datasheet - Page 96

• Manufacturer Part Number: mc9s08dz32amlfr
• Description: Hcs08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

1
2
Chapter 5 Resets, Interrupts, and General System Control
5.8.4
This high page register is a write-once register so only the first write after reset is honored. It can be read
at any time. Any subsequent attempt to write to SOPT1 (intentionally or unintentionally) is ignored to
avoid accidental changes to these sensitive settings. This register should be written during the user’s reset
initialization program to set the desired controls even if the desired settings are the same as the reset
settings.
96
COPT[1:0]
Windowed COP operation requires the user to clear the COP timer in the last 25% of the selected timeout period. This column
displays the minimum number of clock counts required before the COP timer can be reset when in windowed COP mode
(COPW = 1).
Values shown in milliseconds based on t
tolerance of this value.
Reset:
SCI2PS
STOPE
IIC1PS
COPCLKS
Field
7:6
5
4
3
W
N/A
R
0
0
0
1
1
1
Control Bits
System Options Register 1 (SOPT1)
COP Watchdog Timeout — These write-once bits select the timeout period of the COP. COPT along with
COPCLKS in SOPT2 defines the COP timeout period. See
Stop Mode Enable — This write-once bit is used to enable stop mode. If stop mode is disabled and a user
program attempts to execute a STOP instruction, an illegal opcode reset is forced.
0 Stop mode disabled.
1 Stop mode enabled.
SCI2 Pin Select— This write-once bit selects the location of the RxD2 and TxD2 pins of the SCI2 module.
0 TxD2 on PTF0, RxD2 on PTF1.
1 TxD2 on PTE6, RxD2 on PTE7.
IIC1 Pin Select— This write-once bit selects the location of the SCL1 and SDA1 pins of the IIC1 module.
0 SCL1 on PTF2, SDA1 on PTF3.
1 SCL1 on PTE4, SDA1 on PTE5.
1
7
COPT
COPT[1:0]
= Unimplemented or Reserved
0:0
0:1
1:0
1:1
0:1
1:0
1:1
1
6
Figure 5-5. System Options Register 1 (SOPT1)
Table 5-5. SOPT1 Register Field Descriptions
Clock Source
Table 5-6. COP Configuration Options
MC9S08DZ128 Series Data Sheet, Rev. 1
LPO
STOPE
1 kHz
1 kHz
1 kHz
0
N/A
Bus
Bus
Bus
5
= 1 ms. See t
SCI2PS
COP Window
LPO
0
4
196,608 cycles
49,152 cycles
Description
(COPW = 1)
6144 cycles
in the appendix
N/A
N/A
N/A
N/A
IIC1PS
1
Table
Opens
3
0
5-6.
Section A.12.1, “Control
0
0
2
COP Overflow Count
2
2
2
10
8
5
COP is disabled
cycles (256 ms
cycles (32 ms
cycles (1.024 s
2
2
2
Freescale Semiconductor
13
16
18
cycles
cycles
cycles
0
0
1
Timing,” for the
2
1
1
)
)
)
0
0
0