mc9s08dz32amlfr Freescale Semiconductor, Inc, mc9s08dz32amlfr Datasheet - Page 407

• Manufacturer Part Number: mc9s08dz32amlfr
• Description: Hcs08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

18.3.3.14 Debug Trigger Register (DBGT)
1
2
Freescale Semiconductor
end-run
Module Base + 0x000D
The DBG trigger register (DBGT) can not be changed unless ARM=0.
end-run
or non-
In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the control bits in this register do not change after reset.
TRGSEL
Reset
BEGIN
Field
POR
TRG
3–0
W
7
6
R
2
1
TRGSEL
Trigger Selection Bit — The TRGSEL bit controls the triggering condition for the comparators. See
Section 18.4.4, “Trigger Break Control (TBC)”
0 Trigger on any compare address access
1 Trigger if opcode at compare address is executed
Begin/End Trigger Bit — The BEGIN bit controls whether the trigger begins or ends storing of data in FIFO.
0 Trigger at end of stored data
1 Trigger before storing data
Trigger Mode Bits — The TRG bits select the trigger mode of the DBG module as shown in
U
0
7
= Unimplemented or Reserved
BEGIN
U
1
6
Figure 18-15. Debug Trigger Register (DBGT)
TRG Value
Table 18-16. DBGT Field Descriptions
MC9S08DZ128 Series Data Sheet, Rev. 1
Table 18-17. Trigger Mode Encoding
0000
0001
0010
0011
0100
0101
0110
0111
1000
0
0
0
5
A And Not B (Full mode)
0
0
0
4
for more information.
A Then Event Only B
A And B (Full Mode)
Description
Outside Range
Event Only B
Inside Range
A Then B
Meaning
A Only
A Or B
U
0
3
Chapter 18 Debug Module (S08DBGV3) (128K)
U
0
2
TRG
U
0
1
Table
18-17.
U
0
0
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