mc9s08dz32amlfr Freescale Semiconductor, Inc, mc9s08dz32amlfr Datasheet - Page 173

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mc9s08dz32amlfr

Manufacturer Part Number
mc9s08dz32amlfr
Description
Hcs08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
8.3.3
Freescale Semiconductor
1
Field
TRIM
7:0
A value for TRIM is loaded during reset from a factory programmed location when not in any BDM mode. If in a BDM
mode, a default value of 0x80 is loaded.
W
R
MCG Trim Register (MCGTRM)
MCG Trim Setting — Controls the internal reference clock frequency by controlling the internal reference clock
period. The TRIM bits are binary weighted (i.e., bit 1 will adjust twice as much as bit 0). Increasing the binary
value in TRIM will increase the period, and decreasing the value will decrease the period.
An additional fine trim bit is available in MCGSC as the FTRIM bit.
If a TRIM[7:0] value stored in nonvolatile memory is to be used, it’s the user’s responsibility to copy that value
from the nonvolatile memory location to this register.
7
Table 8-5. MCG Trim Register Field Descriptions
6
Figure 8-5. MCG Trim Register (MCGTRM)
MC9S08DZ128 Series Data Sheet, Rev. 1
5
4
Description
TRIM
1
Chapter 8 Multi-Purpose Clock Generator (S08MCGV2)
3
2
1
0
173

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