mc9s08dz32amlfr Freescale Semiconductor, Inc, mc9s08dz32amlfr Datasheet - Page 188

• Manufacturer Part Number: mc9s08dz32amlfr
• Description: Hcs08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 8 Multi-Purpose Clock Generator (S08MCGV2)
This section will include 3 mode switching examples using an 8 MHz external crystal. If using an external
clock source less than 1 MHz, the MCG should not be configured for any of the PLL modes (PEE and
PBE).
8.5.3.1
In this example, the MCG will move through the proper operational modes from FEI to PEE mode until
the 8 MHz crystal reference frequency is set to achieve a bus frequency of 16 MHz. Because the MCG is
in FEI mode out of reset, this example also shows how to initialize the MCG for PEE mode out of reset.
First, the code sequence will be described. Then a flowchart will be included which illustrates the
sequence.
188
1. First, FEI must transition to FBE mode:
2. Then, FBE must transition either directly to PBE mode or first through BLPE mode and then to
1
a) MCGC2 = 0x36 (%00110110)
b) Loop until OSCINIT (bit 1) in MCGSC is 1, indicating the crystal selected by the EREFS bit
c) Because RANGE = 1, set DIV32 (bit 4) in MCGC3 to allow access to the proper RDIV bits
d) MCGC1 = 0x98 (%10011000)
e) Loop until IREFST (bit 4) in MCGSC is 0, indicating the external reference is the current
f) Loop until CLKST (bits 3 and 2) in MCGSC is %10, indicating that the external reference
PBE mode:
R is the reference divider selected by the RDIV bits, B is the bus frequency divider selected by the BDIV bits,
F is the FLL factor selected by the DRS and DMX32 bits, and M is the multiplier selected by the VDIV bits.
– BDIV (bits 7 and 6) set to %00, or divide-by-1
– RANGE (bit 5) set to 1 because the frequency of 8 MHz is within the high frequency range
– HGO (bit 4) set to 1 to configure external oscillator for high gain operation
– EREFS (bit 2) set to 1, because a crystal is being used
– ERCLKEN (bit 1) set to 1 to ensure the external reference clock is active
has been initialized.
while in an FLL external mode.
– CLKS (bits 7 and 6) set to %10 in order to select external reference clock as system clock
– RDIV (bits 5-3) set to %011, or divide-by-256 because 8MHz / 256 = 31.25 kHz which is
– IREFS (bit 2) cleared to 0, selecting the external reference clock
source for the reference clock
clock is selected to feed MCGOUT
Example # 1: Moving from FEI to PEE Mode: External Crystal = 8 MHz,
Bus Frequency = 16 MHz
source
in the 31.25 kHz to 39.0625 kHz range required by the FLL
MC9S08DZ128 Series Data Sheet, Rev. 1
Freescale Semiconductor