mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 141

• Manufacturer Part Number: mc9s12vr48
• Description: S12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

4.3.2.9
This register controls the COP (Computer Operating Properly) watchdog.
The clock source for the COP is either ACLK, IRCCLK or OSCCLK depending on the setting of the
COPOSCSEL0 and COPOSCSEL1 bit (see also
In Stop Mode with PSTP=1 (Pseudo Stop Mode), COPOSCSEL0=1 and COPOSCEL1=0 and PCE=1 the
COP continues to run, else the COP counter halts in Stop Mode with COPOSCSEL1 =0.
In Full Stop Mode and Pseudo Stop Mode with COPOSCSEL1=1 the COP continues to run.
Read: Anytime
Write:
When a non-zero value is loaded from Flash to CR[2:0] the COP time-out period is started.
A change of the COPOSCSEL0 or COPOSCSEL1 bit (writing a different value) or loosing UPOSC status
while COPOSCSEL1 is clear and COPOSCSEL0 is set, re-starts the COP time-out period.
In Normal Mode the COP time-out period is restarted if either of these conditions is true:
In Special Mode, any write access to CPMUCOP register restarts the COP time-out period.
Freescale Semiconductor
0x003C
After de-assert of System Reset the values are automatically loaded from the Flash memory. See Device specification for
Reset
1. RSBCK: Anytime in Special Mode; write to “1” but not to “0” in Normal Mode
2. WCOP, CR2, CR1, CR0:
1. Writing a non-zero value to CR[2:0] (anytime in special mode, once in normal mode) with
2. Writing WCOP bit (anytime in Special Mode, once in Normal Mode) with WRTMASK = 0.
3. Changing RSBCK bit from “0” to “1”.
details.
W
R
— Anytime in Special Mode, when WRTMASK is 0, otherwise it has no effect
— Write once in Normal Mode, when WRTMASK is 0, otherwise it has no effect.
WRTMASK = 0.
– Writing CR[2:0] to “000” has no effect, but counts for the “write once” condition.
– Writing WCOP to “0” has no effect, but counts for the “write once” condition.
WCOP
S12CPMU_UHV COP Control Register (CPMUCOP)
F
7
= Unimplemented or Reserved
Figure 4-12. S12CPMU_UHV COP Control Register (CPMUCOP)
RSBCK
0
6
MC9S12VR Family Reference Manual, Rev. 2.2
Preliminary - Subject to Change Without Notice
WRTMASK
0
0
5
Table
0
0
4
4-6).
Clock, Reset and Power Management (S12CPMU_UHV)
0
0
3
CR2
F
2
CR1
F
1
CR0
F
0
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