mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 154

• Manufacturer Part Number: mc9s12vr48
• Description: S12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Clock, Reset and Power Management (S12CPMU_UHV)
4.3.2.19
The CPMUHTTR register configures the trimming of the S12CPMU_UHV temperature sense.
Read: Anytime
Write: Anytime
154
0x02F7
HTTR[3:0]
After de-assert of System Reset a trim value is automatically loaded from the Flash memory. See Device specification for
Reset
HTOE
Field
details.
3–0
7
W
R
HTOE
High Temperature Offset Enable Bit — If set the temperature sense offset is enabled.
0 The temperature sense offset is disabled. HTTR[3:0] bits don’t care.
1 The temperature sense offset is enabled. HTTR[3:0] select the temperature offset.
High Temperature Trimming Register (CPMUHTTR)
High Temperature Trimming Bits — See
0
7
= Unimplemented or Reserved
Figure 4-25. High Temperature Trimming Register (CPMUHTTR)
HTTR[3]
HTTR[2]
HTTR[1]
HTTR[0]
0
0
6
Bit
Table 4-23. CPMUHTTR Field Descriptions
MC9S12VR Family Reference Manual,
Preliminary - Subject to Change Without Notice
Table 4-24. Trimming Effect of HTTR
Increases V
Increases V
Increases V
Increases V
0
0
5
HT
HT
HT
HT
twice of HTTR[2]
twice of HTTR[1]
twice of HTTR[0]
(to compensate Temperature Offset)
Table 4-24
0
0
4
Trimming Effect
Description
for trimming effects.
HTTR3
F
3
Rev. 2.2
HTTR2
F
2
HTTR1
Freescale Semiconductor
F
1
HTTR0
F
0