mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 350

• Manufacturer Part Number: mc9s12vr48
• Description: S12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Serial Peripheral Interface (S12SPIV5)
11.3.2.2
Read: Anytime
Write: Anytime; writes to the reserved bits have no effect
350
Module Base +0x0001
Reset
LSBFE
SSOE
Field
1
0
W
R
Slave Select Output Enable — The SS output feature is enabled only in master mode, if MODFEN is set, by
asserting the SSOE as shown in
progress and force the SPI system into idle state.
LSB-First Enable — This bit does not affect the position of the MSB and LSB in the data register. Reads and
writes of the data register always have the MSB in the highest bit position. In master mode, a change of this bit
will abort a transmission in progress and force the SPI system into idle state.
0 Data is transferred most significant bit first.
1 Data is transferred least significant bit first.
SPI Control Register 2 (SPICR2)
0
0
7
MODFEN
= Unimplemented or Reserved
0
0
1
1
XFRW
0
6
Table 11-2. SPICR1 Field Descriptions (continued)
SSOE
Figure 11-4. SPI Control Register 2 (SPICR2)
MC9S12VR Family Reference Manual,
0
1
0
1
Preliminary - Subject to Change Without Notice
Table 11-3. SS Input / Output Selection
0
0
5
Table
SS input with MODF feature
11-3. In master mode, a change of this bit will abort a transmission in
SS is slave select output
MODFEN
SS not used by SPI
SS not used by SPI
Master Mode
0
4
Description
BIDIROE
0
3
Rev. 2.2
0
0
2
Slave Mode
SS input
SS input
SS input
SS input
SPISWAI
Freescale Semiconductor
0
1
SPC0
0
0