mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 177

• Manufacturer Part Number: mc9s12vr48
• Description: S12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

5.1.3
A block diagram of the BDM is shown in
5.2
A single-wire interface pin called the background debug interface (BKGD) pin is used to communicate
with the BDM system. During reset, this pin is a mode select input which selects between normal and
special modes of operation. After reset, this pin becomes the dedicated serial interface pin for the
background debug mode.
(CPMUSYNR). The BDM clock frequency is always VCO clock frequency divided by 8. After reset the
BDM clock is based on the reset values of the CPMUSYNR register (4 MHz). When modifying the VCO
clock please make sure that the communication rate is adapted accordingly and a communication time-out
(BDM soft reset) has occurred.
5.3
5.3.1
Table 5-2
Freescale Semiconductor
System
Host
External Signal Description
Memory Map and Register Definition
shows the BDM memory map when BDM is active.
Block Diagram
Module Memory Map
Register Block
BKGD
BDMSTS
Register
BDMACT
ENBDM
UNSEC
TRACE
SDV
Interface
The communication rate of this pin is based on the settings for the VCO clock
Serial
MC9S12VR Family Reference Manual, Rev. 2.2
Preliminary - Subject to Change Without Notice
Control
Data
Figure 5-1. BDM Block Diagram
Figure
Standard BDM Firmware
16-Bit Shift Register
Secured BDM Firmware
Instruction Code
LOOKUP TABLE
LOOKUP TABLE
5-1.
Execution
and
Background Debug Module (S12SBDMV1)
Bus Interface
Control Logic
and
Address
Data
Control
Clocks
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