mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 151

• Manufacturer Part Number: mc9s12vr48
• Description: S12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

4.3.2.17
The CPMUAPIRH and CPMUAPIRL registers allow the configuration of the autonomous periodical
interrupt rate.
Read: Anytime
Write: Anytime if APIFE=0, Else writes have no effect.
The period can be calculated as follows depending on logical value of the APICLK bit:
Freescale Semiconductor
0x02F4
0x02F5
APIR[15:0]
Reset
Reset
Field
15-0
W
W
R
R
APICLK=0: Period = 2*(APIR[15:0] + 1) * (ACLK Clock Period * 2)
APICLK=1: Period = 2*(APIR[15:0] + 1) * Bus Clock Period
APIR15
APIR7
Autonomous Periodical Interrupt Rate Bits — These bits define the time-out period of the API. See
Table 4-21
Figure 4-22. Autonomous Periodical Interrupt Rate High Register (CPMUAPIRH)
Autonomous Periodical Interrupt Rate High and Low Register
(CPMUAPIRH / CPMUAPIRL)
Figure 4-23. Autonomous Periodical Interrupt Rate Low Register (CPMUAPIRL)
0
0
7
7
For APICLK bit clear the first time-out period of the API will show a latency
time between two to three f
release when the API feature gets enabled (APIFE bit set)
= Unimplemented or Reserved
for details of the effect of the autonomous periodical interrupt rate bits.
APIR14
APIR6
Table 4-20. CPMUAPIRH / CPMUAPIRL Field Descriptions
0
0
6
6
MC9S12VR Family Reference Manual, Rev. 2.2
Preliminary - Subject to Change Without Notice
APIR13
APIR5
0
0
5
5
ACLK
APIR12
APIR4
cycles due to synchronous clock gate
NOTE
0
0
4
4
Description
APIR11
APIR3
Clock, Reset and Power Management (S12CPMU_UHV)
0
0
3
3
APIR10
APIR2
.
0
0
2
2
APIR9
APIR1
0
0
1
1
APIR8
APIR0
0
0
0
0
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