mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 57

• Manufacturer Part Number: mc9s12vr48
• Description: S12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

1
1
2.3.3
2.3.4
Freescale Semiconductor
Function
Address 0x0008
Address 0x0009
Read: Anytime. The data source is depending on the data direction value.
Write: Anytime
Read: Anytime
Write: Anytime
Altern.
Field
Reset
Reset
PE
PE
1
0
W
W
R
R
PorT data register port E — General-purpose input/output data, CPMU OSC XTAL signal
If the CPMU OSC function is active this pin is used as XTAL signal and the pulldown device is
disabled. When not used with the alternative function, this pin can be used as general-purpose I/O.
In general-purpose output mode the register bit is driven to the pin.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
synchronized pin input state is read.
PorT data register port E — General-purpose input/output data, CPMU OSC EXTAL signal
If the CPMU OSC function is active this pin is used as EXTAL signal and the pulldown device is
disabled. When not used with the alternative function, this pin can be used as general-purpose I/O.
In general-purpose output mode the register bit is driven to the pin.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
synchronized pin input state is read.
• The CPMU OSC function takes precedence over the general purpose I/O function if enabled.
• The CPMU OSC function takes precedence over the general purpose I/O function if enabled.
Port E Data Register (PORTE)
Port E Data Direction Register (DDRE)
—
0
0
0
0
7
7
—
0
0
0
0
6
6
Figure 2-2. Port E Data Direction Register (DDRE)
Table 2-4. PORTE Register Field Descriptions
MC9S12VR Family Reference Manual, Rev. 2.2
Figure 2-1. Port E Data Register (PORTE)
Preliminary - Subject to Change Without Notice
—
5
0
0
5
0
0
—
0
0
0
0
4
4
Description
—
0
0
0
0
3
3
—
Port Integration Module (S12VRPIMV2)
0
0
0
0
2
2
DDRE1
Access: User read/write
Access: User read/write
XTAL
PE1
0
0
1
1
DDRE0
EXTAL
PE0
0
0
0
0
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1
1