cx29600 Mindspeed Technologies, cx29600 Datasheet - Page 132

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cx29600

Manufacturer Part Number
cx29600
Description
Optiphytm - M155 Sts-3 Sonet/sdh Multiplexer
Manufacturer
Mindspeed Technologies
Datasheet
4.0 Registers
4.1 Memory Map
ENSEC (Receive Section Interrupt Mask Control Register)
The ENSEC register controls section interrupt enables.
ENSUMINT (Summary Interrupt Mask Control Register)
The ENSUMINT register determines which of the interrupts listed in SUMINT are observed on MIntr*.
4-26
7-6
Bit
Bit
7
6
5
4
3
2
1
0
5
4
3
2
1
0
Default
Default
00
0
0
0
0
0
0
0
0
0
0
0
hex address: 0x038
hex address: 0x004
EnOneSecInt
EnPLLRefInt
EnSecTrace
EnPort1Int
EnSigDet
EnF1Intr
Mindspeed Technologies
EnB1Err
EnLOS
EnLOL
EnLOF
Name
EnSEF
Name
This bit enables the Signal Detect interrupt.
This bit enables the Loss of Lock interrupt.
This bit enables the Loss of Signal interrupt.
This bit enables the Out of Frame interrupt.
This bit enables the Loss of Frame interrupt.
This bit enables the Section BIP Error interrupt.
This bit enables the Section Trace interrupt.
This bit enables the F1 byte change interrupt.
Reserved, set to zero.
Enables the PLL Reference status interrupt to appear on the MIntr*
pin.
Enables the One Second Interrupt to appear on the MIntr* pin.
Reserved.
Reserved.
Reserved.
This bit is a global enable for Port1 interrupt sources when set to 1.
Description
Description
CX29600 Data Sheet
29600-DSH-001-B
CX29600

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