cx29600 Mindspeed Technologies, cx29600 Datasheet - Page 82

• Manufacturer Part Number: cx29600
• Description: Optiphytm - M155 Sts-3 Sonet/sdh Multiplexer
• Manufacturer: Mindspeed Technologies

2.0 Functional Description
2.5 Microprocessor Interface
2.5.4 One-second Latching
2-38
Mindspeed’s implementation of one-second latching assures the integrity of the
statistics being gathered by the network management software. Internal statistics
counters can be latched at one-second intervals, which are synchronized to the
OneSecIn pin. Therefore, the data read from the statistic counters represents the
same “one second” of real-time data, independent of network management
software timing.
counter values. When EnStatLat (bit 5) in the GEN register is written to a logic 1,
a read from any of the status registers will return the state of the device at the time
of the previous OneSecIn pin assertion. When the EnCntrLat bit (4) in the GEN
register is written to a logic 1, a read from any of the counters returns the state of
the device at the time of the previous OneSecIn pin assertion. Every second, the
counter is read, moved to the latch, and cleared.
be achieved by connecting the OneSecIn pin to the OneSecOut pin. The
OneSecOut signal is derived from the 8kHzIn pin. This signal is asserted for one
8kHzIn clock period, every 8,000 8kHzIn periods. If 8kHzIn is being driven by
an 8 kHz clock, the OneSecOut signal is asserted every second.
NOTE:
The CX29600 implements one-second latching for both status signals and
The OneSecIn pin is intended to be asserted at one-second intervals. This can
When latching is disabled and a counter is wider than one byte, the LSB
should be read first, which will retain the values of the other bytes for a
subsequent read.
Mindspeed Technologies
™
CX29600 Data Sheet
29600-DSH-001-B
CX29600