cx29600 Mindspeed Technologies, cx29600 Datasheet - Page 52

• Manufacturer Part Number: cx29600
• Description: Optiphytm - M155 Sts-3 Sonet/sdh Multiplexer
• Manufacturer: Mindspeed Technologies

2.0 Functional Description
2.2 Clock Circuits
Table 2-3. Transmit/Receive Default Clock Configuration
2-8
Internal CDR enabled
Transmit clock synthesized from 19.44 MHz
reference input (LTxSynRef pin)
LTxData sourced from transmit framer
Receive data from LRxData +/- inputs
PECL line loopback disabled
Local source loopback disabled
LTxData buffer enabled
LTxClk buffer power down enabled
CDR charge pump frequency - 622 MHz
Transmit clock synthesizer enabled
CDR PLL hysteresis values
Configuration Description
selections for loopback capabilies. The available loopback modes are described in
Section
of the the line interface for the OC-12 SONET mode. This is the default mode of
operation upon device reset. The control registers shown in
The line interface circuits of the CX29600 provide many clock and data path
Table 2-3
2.8.
Mindspeed Technologies
CLKREC[5]
CLKREC[4:3]
CLKREC[2]
CLKREC[1]
CLKREC[0]
CLKRECPD[6]
CLKRECPD[4]
CLKRECPD[3]
TESTMODE[7]
TESTMODE[6]
WINHYST1_L
shows the register bits which are required for proper configuration
Control Register and
Bit Position Index
WINHYST
ExtClkRec = 0
TxClkSel[1:0] = 00
TxDataSel = 0
SrcLoop = 0
NELnLoop = 0
LclSrcLoop = 0
PD_Data = 0
PD_Clk = 1
Speed_CP = 1
Pd_TxSyn = 0
Register Bit Names
™
and Values
Figures 2-5
CLKREC = 0x00
CLKRECPD = 0x08
TESTMODE = 0x80
CX29600 Data Sheet
Default Register
29600-DSH-001-B
Value
and 2-6.
CX29600