cx29600 Mindspeed Technologies, cx29600 Datasheet - Page 77

• Manufacturer Part Number: cx29600
• Description: Optiphytm - M155 Sts-3 Sonet/sdh Multiplexer
• Manufacturer: Mindspeed Technologies

CX29600
CX29600 Data Sheet
2.4.4 Path Overhead
Table 2-19. Path Overhead Transmit and Receive Functions
29600-DSH-001-B
2.4.4.2 B3
2.4.4.1 J1
RxE2 output pin.
Path overhead can either be generated by CX29600 or taken from the path
overhead presented in the STS-1 inputs from the SI-Bus interface. Internal
generation is the default, but each overhead octet can be individually selected as
either internally generated or sourced from the SI-Bus interface by the bits in the
PTHINS register.
Section and Line Overhead must be terminated before the Path Overhead can be
accessed.
Overhead.
The Path Trace byte, J1, is a circular 64-byte buffer, carrying the Path Trace
message, so that a receiving Path Terminating Equipment (PTE) can verify
continued connection to the transmitting PTE. This buffer overwrites when full.
This byte is set to 00h as the default. If TXPTH bit 7 is set high, then the J1 byte
will contain a 64-byte circular message extracted from the TXPTHBUF RAM
space. If PTHINSL bit 7 is high, then J1 will contain the contents as received on
the SI-Bus interface regardless of the settings of other control bits affecting J1.
microprocessor interface. A maskable interrupt (PTHINT bit 0) is generated
when the incoming message differs from the previous buffer contents.
The Path BIP-8 byte, B3, is allocated for path error monitoring. Errors are
reported in RXPTH bit 4 and counted in B3CNT. The counter length is 16 bits so
that saturation does not occur during a one-second latching interval. B3 carries
the BIP-8 calculation for path error monitoring as the default. If TXPTH bit 6 is
set high, the B3 byte will contain 00h. If PTHINSH bit 3 is set high, the normal
B3 byte value (by calculation or 00h as determined by TXPTH bit 6) will be
XORed with the value contained in the ERRPAT register before transmission. If
PTHINSL bit 6 is high, then B3 will contain the contents as received on the
SI-Bus interface regardless of the settings of other control bits affecting B3
(except error insertion will work on any B3 source).
Uneq-P conditions.
The E2 byte is latched from the receive stream and then shifted out to the
The Path Overhead checks for end-to-end communication integrity. The
The J1 byte is captured into a 64-byte circular buffer that is readable from the
B3 BIP counts are disabled during LOS, LOF, AIS-L, AIS-P, LOP-P, or
Byte
B3
C2
G1
J1
Mindspeed Technologies
Table 2-19
00 hex or 64-byte trace buffer
Calculated, error insertion
From the TXC2 register
Path FEBE, RDI inserted
lists the transmit and receive functions of the Path
Transmit
2.4 SONET/SDH Framer and Overhead Processor
™
Monitor Rx trace buffer, interrupt on
change
Checked, errors counted
Compared to PROVC2
Checked, errors counted, status
2.0 Functional Description
Receive
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