cx29600 Mindspeed Technologies, cx29600 Datasheet - Page 79

• Manufacturer Part Number: cx29600
• Description: Optiphytm - M155 Sts-3 Sonet/sdh Multiplexer
• Manufacturer: Mindspeed Technologies

CX29600
CX29600 Data Sheet
29600-DSH-001-B
2.4.4.9 N1 (Z5)
2.4.4.8 K3 (Z4)
2.4.4.7 F3 (Z3)
2.4.4.6 H4
2.4.4.5 F2
Table 2-21. G1 bit Indications
The F2 byte is allocated for user communication purposes between STS Path
terminating NEs. F2 is set to the value contained in the TXF2 register. If
PTHINSL bit 3 is high, then F2 will contain the contents as received on the
SI-Bus interface.
maskable interrupt (PNTRINT bit 3) is generated when the incoming F2 byte
differs consistently from the current value for 3 consecutive frames.
The H4 byte is allocated for use as a mapping-specific indicator byte. H4 is set to
00h as the default. If PTHINSL bit 2 is high, then H4 will contain the contents as
received on the SI-Bus interface.
and third STS-1 positions when the data is transferred downstream.
The F3 (Z3) byte is allocated for future growth, and is set to the value of the
TXF3 register. If PTHINSL bit 1 is high, then F3 will contain the contents as
received on the SI-Bus interface.
maskable interrupt (PNTRINT bit 2) is generated when the incoming F3 byte
differs consistently from the current value for 3 consecutive frames.
The K3 (Z4) byte is allocated for future growth, and is set to the value of the
TXK3 register. If PTHINSL bit 0 is high, then K3 will contain the contents as
received on the SI-Bus interface.
maskable interrupt (PNTRINT bit 1) is generated when the incoming K3 byte
differs consistently from the current value for 3 consecutive frames.
The N1 (Z5) byte is allocated for Tandem Connection Maintenance and the Path
Data Channel, and is set to the value of the TXN1 register. If PTHINSH bit 6 is
high, then N1 bits 1–4 will contain the incoming B3 error count value from the
receiver (or signal fail indication) for use with tandem connections. If PTHINSH
bit 7 is high, then N1 bits 1–4 will contain the contents as received on the SI-Bus
interface. If bits 7 and 6 are high, then N1 bits 1–4 will contain 1111. If
PTHINSH bit 5 is high, then N1 bits 5–8 will contain the contents as received on
the SI-Bus interface.
access. Bits 1–4 are also monitored for ISF status and tandem connection error
counts. A maskable interrupt (PNTRINT bit 0) is generated when ISF
(IEC=1111) is detected or when a tandem error count is detected.
The F2 byte is latched in to the RXF2 register for processor access. A
The H4 byte from the first STS-1 position can be replicated into the second
The F3 (Z3) byte is latched in to the RXF3 register for processor access. A
The K3 (Z4) byte is latched in to the RXK3 register for processor access. A
The N1(Z5) byte is latched in to the RXN1 register each frame for processor
AutoRDI-P
1
1
1
1
Mindspeed Technologies
LOS, LOF, AIS-L, AIS-P, LOP-P
UNEQ-P
PLM-P
No defects
Trigger
2.4 SONET/SDH Framer and Overhead Processor
™
101 for a minimum of 20 frames.
110 for a minimum of 20 frames.
010 for a minimum of 20 frames.
001 for a minimum of 20 frames.
2.0 Functional Description
G1 bits 5, 6, 7
2-35