cx29600 Mindspeed Technologies, cx29600 Datasheet - Page 81

• Manufacturer Part Number: cx29600
• Description: Optiphytm - M155 Sts-3 Sonet/sdh Multiplexer
• Manufacturer: Mindspeed Technologies

CX29600
CX29600 Data Sheet
2.5.1 Interface Modes
2.5.2 Status and Control
2.5.3 Counters
29600-DSH-001-B
2.5 Microprocessor Interface
The CX29600 microprocessor interface can operate in one of two modes. The
Mindspeed EBUS mode is normally selected when the device is used in
applications with the CX29503/CX29513 and the CX28500/CX28560. The
EBUS mode has a multiplexed address and data bus, and seperate read and write
control signals. See Table 1-4 for the interface signal descriptions. Read and write
cycle timing diagrams are shown in
MPC860 style interface. This interface has seperate address and data lines with a
single read/write signal. Table 1-4 describes the interface signal descriptions.
Figures 5-5
Several registers provide status and control information to the microprocessor.
Status information includes interrupts, counters, and generic functional status.
Control information includes configuration and real-time control, according to
the specific function of each control register. There are two types of status input:
live and latched. Live status provides the current status of the device. Latched
status is used for rapidly changing states in order to capture information until it
can be read.
master reset, output status, and device part number and revision. The
software-controlled master reset, GEN register (0x00) bit 0, restarts all device
functions and sets the control and status registers to their default values. The
OUTSTAT register (0x02) provides a means for controlling external devices via
the OutStat pins. It is enabled by setting the StatPinMode (bit 2) of the GEN
register (0x00). The VER register (0x03) uniquely identifies the device and
revision level.
The CX29600 counters are used to record events within the device. There are two
types of events: error events, such as Section BIP errors, and transmission events.
reading the least significant byte first. This guarantees that the value contained in
each component register accurately reflects the composite counter value at the
time the least significant byte was read. This is important because the counter
may be updated while the component registers are being read.
that may occur within a one-second interval. The counters are cleared after being
read. Therefore, if the counters are read every second, the application receives an
accurate recording of all event occurrences.
The MPC860 interface mode allows easy glueless connectivity to a Motorola
The CX29600 contains general purpose status and control functions, such as a
Counters which are composed of more than one register must be accessed by
Each counter is large enough to accommodate the maximum number of events
Mindspeed Technologies
and
5-6
illustrate the read and write cycle timing.
Figures 5-5
™
and 5-6.
2.0 Functional Description
2.5 Microprocessor Interface
2-37