w65c51n Western Design Center, Inc., w65c51n Datasheet - Page 10

• Manufacturer Part Number: w65c51n
• Description: Asynchronous Communications Interface Adapter Acia
• Manufacturer: Western Design Center, Inc.

COMMAND REGISTER
The Command Register controls specific modes and functions
Reset Initialization
7
0
-
PMC1
Bits 7-6
Bit 5
Bit 4
Bits 3-2
Bit 1
Bit 0
3
0
0
1
1
7
7
0
0
1
1
0
1
0
1
0
1
0
1
6
0
-
PMC
5
0
2
0
1
0
1
-
PMC0
Parity Mode Enabled (PME)
Parity mode disabled
Parity check and parity transmission disabled
Parity mode enabled and Mark parity bit always transmitted
(See Errata, pg. 33)
Receiver Echo Mode (REM)
Receiver normal mode
Receiver echo mode bits 2 and 3
Must be zero for receiver echo
mode, RTS will be low
Receiver Interrupt Request Disabled
(IRD)
IRQB enabled
IRQB disabled
Data Terminal Ready (DTR)
Data terminal not ready (DTRB
high)
Data terminal ready (DTRB low)
6
4
0
0
6
0
1
0
1
Transmitter Interrupt Control (TIC)
RTSB = High, transmit interrupt
disabled
RTSB = Low, transmit interrupt
enabled
RTSB = Low, transmit interrupt
disabled
RTSB = Low, transmit interrupt
disabled
Transmit break on TxD
3
0
0
PME
5
Parity Mode Control (PMC)
Receiver Odd parity checked
Receiver Even parity checked
Receiver Parity check disabled
Receiver Parity check disabled
2
0
0
REM
1
0
0
4
0
0
0
TIC1
3
Hardware reset (RESB)
Program reset
TIC
TIC0
2
IRD
1
DTR
0
10