w65c51n Western Design Center, Inc., w65c51n Datasheet - Page 15

• Manufacturer Part Number: w65c51n
• Description: Asynchronous Communications Interface Adapter Acia
• Manufacturer: Western Design Center, Inc.

TRANSMITTER AND RECEIVER OPERATION
Continuous Data Transmit
In the normal operating mode, the interrupt request output (IRQB) signals when the ACIA is ready to
accept the next data word to be transmitted. This interrupt occurs at the beginning of the Start Bit. When
the processor reads the Status Register of the ACIA, the interrupt is cleared.
The processor must then identify that the Transmit Data Register is ready to be loaded and must then
load it with the next data word. This must occur before the end of the Stop Bit, otherwise a continuous
“MARK” will be transmitted.
Continuous Data Receive
Similar to the Continuous Data Transmit case, the normal operation of this mode is to assert IRQB when
the ACIA has received a full data word. This occurs at about the 9/16 point through the Stop Bit. The
processor must read the Status Register and read the data word before the next interrupt, otherwise the
Overrun condition occurs.
IRQB
IRQB
TxD
RxD
PROCESSOR INTERRUPT
(TRANSMIT DATA
REGISTER EMPTY)
PROCESSOR INTERRUPT
OCCURS ABOUT 9/16
INTO LAST STOP BIT.
PARITY, OVERRUN AND
FRAMING ERROR ALSO
UPDATED
Start
Start
B
B
0
0
CHAR # n
CHAR # n
B
B
1
1
B
B
N
N
P
P
Stop
Stop
PROCESSOR READS
STATUS REGISTER,
CAUSES IRQB TO CLEAR.
PROCESSOR READS
STATUS REGISTER,
CAUSES IRQB TO CLEAR.
Figure 6 shows the continuous Data Receive Timing Relationship.
Start
Start
Figure 5 shows the Continuous Data Transmit timing relationship.
Figure 5 Continuous Data Transmit
B
B
Figure 6 Continuous Data Receive
0
0
CHAR # n+1
CHAR # n+1
B
B
1
1
B
B
N
N
P
P
Stop
Stop
Start
Start
PROCESSOR MUST
LOAD NEW DATA IN THIS
TIME INTERVAL;
OTHERWISE,
CONTINUOUS “MARK” IS
TRANSMITTED
PROCESSOR MUST
READ RECEIVER DATA IN
THIS TIME INTERVAL;
OTHERWISE, OVERRUN
OCCURS
B
B
0
0
CHAR # n+2
CHAR # n+2
B
B
1
1
B
B
N
N
P
P
Stop
Stop
Start
Start
B
B
0
0
CHAR # n+3
CHAR # n+3
B
B
1
1
B
B
N
N
P
P
Stop
Stop
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