w65c51n Western Design Center, Inc., w65c51n Datasheet - Page 21

• Manufacturer Part Number: w65c51n
• Description: Asynchronous Communications Interface Adapter Acia
• Manufacturer: Western Design Center, Inc.

Transmit Continuous “BREAK”
This mode is selected via the ACIA Command Register and causes the Transmitter to send continuous
“BREAK” characters, beginning with the next character transmitted. At least one full “BREAK” character
will be transmitted, even if the processor quickly reprograms the Command Register transmit mode.
Later, when the Command Register is programmed back to normal transmit mode, an immediate Stop Bit
will be generated and transmission will resume. Figure 16 shows the timing relationship for this mode.
Note:
If, while operating in the Transmit Continuous “BREAK” mode, the CTSB should go to a high, the TxD will
be overridden by the CTSB and will go to continuous “MARK” at the beginning of the next character
transmitted after the CTSB goes high.
Receive Continuous “BREAK”
In the event the modem transmits continuous “BREAK” characters, the ACIA will terminate receiving.
Reception will resume only after a Stop Bit is encountered by the ACIA. Figure 17 shows the timing
relationship for continuous “BREAK” characters.
IRQB
TxD
RxD
IRQB
NORMAL
INTERRUPT
Stop
B
1
Start
B
0
B
N
B
1
PROCESSOR
INTERRUPT FOR
RECEIVER DATA
REGISTER FULL
P
Stop
B
Start
N
Figure 16 Transmit Continuous “BREAK”
Figure 17 Receive Continuous “BREAK”
P
B
0
Stop
B
1
Start
CONTINUOUS “BREAK”
B
PROCESSOR INTERRUPT
WITH BREAK AND
FRAMING ERROR SET.
EVEN PARITY CHECK WILL
ALSO GIVE A PARITY
ERROR BECAUSE ALL
ZEROS (CONTINUOUS
BREAK) REPRESENT
EVEN PARITY.
0
PERIOD
DURING WHICH
PROCESSOR
SELECTS
CONTINUOUS
“BREAK” MODE
B
N
B
1
P
Stop
B
N
P
NO
MORE
INTERRUPTS
Stop
Stop
POINT AT
WHICH
PROCESSOR
SELECTS
NORMAL
TRANSMIT
MODE
Start
NO INTERRUPT
SINCE
RECEIVER
DISABLED UNTIL
FIRST STOP BIT
Stop
B
0
Start
B
1
B
0
PROCESSOR
INTERRUPT TO
LOAD TRANSMIT
DATA
B
NORMAL
RECEIVER
INTERRUPT
N
B
N
P
P
Stop Start
Stop Start
B
0
B
0
B
1
B
1
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