w65c51n Western Design Center, Inc., w65c51n Datasheet - Page 16

• Manufacturer Part Number: w65c51n
• Description: Asynchronous Communications Interface Adapter Acia
• Manufacturer: Western Design Center, Inc.

Transmit Data Register Not Loaded by Processor
If the processor is unable to load the Transmit Data Register in the allocated time, then the TxD line goes
to the “MARK” condition until the data is loaded. IRQB interrupts continue to occur at the same rate as
previously, yet no data is transmitted. When the processor finally loads new data, a Start Bit immediately
occurs, the data word transmission is started and another interrupt is initiated, signaling for the next data
word. Figure 7 shows the timing relationship for this mode of operation.
Effect of CTSB on Transmitter
CTSB is the Clear-to-Send signal generated by the modem. It is normally low (true state) but may go
high in the event of some modem problems. When this occurs, the TxD line goes to the “MARK”
condition after the entire last character (including parity and stop bit) have been transmitted. Bit 4 in the
Status Register indicates that the Transmitter Data Register is not empty and IRQB is not asserted.
CTSB is transmit control line only, and has not effect on the ACIA Receiver Operation. Figure 8 shows
the timing relationship for this mode of operation.
PROCESSOR
INTERRUPT
FOR DATA
REGISTER
EMPTY
IRQB
CTSB
TxD
IRQB
TxD
CHAR # n
Stop
B
1
PROCESSOR
READS
STATUS
REGISTER
Start
B
B
0
N
CHAR # n
PROCESSOR DOES
NOT LOAD NEW
DATA IN TIME
B
1
P
CLEAR-TO-SEND
Stop
Figure 7 Transmit Data Register Not Loaded by Processor
B
Start
N
P
B
0
Stop
CHAR # n+1
B
Figure 8 Effect of CTS on Transmitter
1
CONTINUOUS “MARK”
CHARACTER
INTERRUPTS
CONTINUE AT
CHARACTER RATE,
EVEN THOUGH
NO DATA IS
TRANSMITTED
TIME
B
N
P
Stop
Start
B
0
Start
CTSB GOES HIGH INDICATING MODEM
IS NOT READY TO RECEIVE DATA, TxD
GOES TO “MARK” CONDITION AFTER
COMPLETE CHARACTER IS
TRANSMITTED
B
1
B
B
2
0
CHAR # n+1
NOT CLEAR-TO-SEND
B
WHEN PROCESSOR FINALLY
LOADS NEW DATA, TRANSMISSION
STARTS IMMEDIATELY AND
INTERRUPT OCCURS, INDICATING
TRANSMIT DATA REGISTER EMPTY
1
B
N
B
P
N
Stop
P
Stop
CONTINUOUS “MARK”
Start
B
0
CHAR # n+2
B
1
IRQB IS NOT ASSERTED
AGAIN UNTIL CTSB
GOES LOW
B
N
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