w65c51n Western Design Center, Inc., w65c51n Datasheet - Page 20

• Manufacturer Part Number: w65c51n
• Description: Asynchronous Communications Interface Adapter Acia
• Manufacturer: Western Design Center, Inc.

Effect of DCDB on Receiver
DCDB is a modem output indicating the status of the carrier-frequency-detection circuit of the modem.
This line goes high for a loss of carrier. Normally, when this occurs, the modem will stop transmitting data
some time later. The ACIA asserts IRQB whenever DCDB changes state and indicates this condition via
bit 5 in the Status Register.
Once such a change of state occurs, subsequent transitions will not cause interrupts or changes in the
Status Register until the first interrupt is serviced. When the Status Register is read by the processor, the
ACIA automatically checks the level of the DCDB line, and if it has changed, another IRQB occurs (see
Figure 14).
Timing with 1½ Stop Bits
It is possible to select 1½ Stop Bits, but this occurs only for 5-bit data words with no parity bit. In this
case, the IRQB asserted for Receiver Data Register Full occurs halfway through the trailing half-Stop Bit.
Figure 15 shows the timing relationship for this mode.
DCDB
RxD
IRQB
B
0
B
1
B
2
B
N
RxD
IRQB
NORMAL
PROCESSOR
INTERRUPT
P
Stop
Start
Start
Figure 14 Effect of DCDB on Receiver
B
PROCESSOR
INTERRUPT
FOR DCDB
GOING HIGH
Figure 15 Timing with 1½ Stop Bits
0
B
CHAR # n
0
B
1
B
1
MODEM
B
DELAY
2
B
2
B
3
PROCESSOR INTERRUPT
OCCURS HALFWAY
THROUGH THE ½ STOP
BIT
AS LONG AS
DCDB IS HIGH,
NO FURTHER
INTERRUPTS
FOR RECEIVER
WILL OCCUR
B
4
1 1/2
Stop
CONTINUOUS “MARK”
Start
B
0
CHAR # n+1
B
1
PROCESSOR
INTERRUPT
FOR DCDB
GOING LOW
B
2
MODEM
DELAY
B
3
B
4
1 1/2
Stop
P
NO INTERRUPT
WILL OCCUR
HERE, SINCE
RECEIVER IS
NOT ENABLED
UNTIL FIRST
START BIT
DETECTED
Stop
Start
B
0
B
1
PROCESSOR
INTERRUPT
FOR
RECEIVER
DATA
B
N
P
P
Stop
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