w65c51n Western Design Center, Inc., w65c51n Datasheet - Page 13

• Manufacturer Part Number: w65c51n
• Description: Asynchronous Communications Interface Adapter Acia
• Manufacturer: Western Design Center, Inc.

The IRQB pin is an interrupt output from the interrupt control logic. It is an open drain output, permitting
several devices to be connected to the common IRQB microprocessor input. Normally a high level, IRQB
goes low when an interrupt occurs.
Data Bus (D0-D7)
The eight data line (D0-D7) pins transfer data between the processor and the ACIA. These lines are bi-
directional and are normally high-impedance except during Read cycles when the ACIA is selected.
Chip Selects (CS0, CS1B)
The two chip select inputs are normally connected to the processor address lines either directly or
through decoders. The ACIA is selected when CS0 is high and CS1B is low. When the ACIA is selected,
the internal registers are addressed in accordance with the register select lines (RS0, RS1).
Register Selects (RS0, RS1)
The two register select lines are normally connected to the processor address lines to allow the processor
to select the various ACIA internal registers. Table 1 shows the internal register select coding.
Only the Command and Control registers can both be read and written. The programmed Reset operation does not
cause any data transfer, but is used to clear bits 4 through 0 in the Command Register and bit 2 in the Status
Register. The Control Register is unchanged by a programmed Reset. It should be noted that the programmed
Reset is slightly different from the hardware Reset (RESB); refer to the register description.
RS1
H
H
L
L
RS0
H
H
L
L
Write Transmit
Data Register
Programmed
Reset (Data is
“Don’t Care”)
Write Command
Register
Write Control
Register
Table 1 ACIA Register Selection
RWB = Low
Register Operation
Read Receiver
Data Register
Read Status
Register
Read Command
Register
Read Control
Register
RWB = High
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