w65c51n Western Design Center, Inc., w65c51n Datasheet - Page 17

• Manufacturer Part Number: w65c51n
• Description: Asynchronous Communications Interface Adapter Acia
• Manufacturer: Western Design Center, Inc.

Effect of Overrun on Receiver
If the processor does not read the Receiver Data Register in the allocated time, then, when the following
interrupt occurs, the new data word is not transferred to the Receiver Data Register, but the Overrun
status bit is set. Thus, the Data Register will contain the last valid data word received and all following
data is lost. Figure 9 shows the timing relationship for this mode.
Echo Mode Timing
In Echo Mode, the TxD line re-transmits the data on the RxD line, delayed by ½ of the bit time, as shown
in Figure 10.
IRQB
IRQB
RxD
PROCESSOR INTERRUPT
FOR RECEIVER DATA
REGISTER FULL
Stop
Start
B
0
CHAR # n
B
1
RxD
TxD
B
N
P
Stop
P
PROCESSOR
READS STATUS
REGISTER
Stop Start
Stop
Start
Figure 9 Effect of Overrun on Receiver
Start
B
PROCESSOR
DOES NOT
READ STATUS
REGISTER
0
B
½ DATA BIT DELAY
B
0
Figure 10 Echo Mode Timing
0
B
1
CHAR # n+1
B
B
1
1
PROCESSOR
DOES NOT
READ DATA
REGISTER
B
N
B
B
N
N
P
P
P
Stop
Stop
Stop Start
Start
Start
B
B
0
B
0
0
CHAR # n+2
B
B
OVERRUN BIT SET IN
STATUS REGISTER
1
1
B
1
RECEIVER DATA REGISTER
NOT UPDATED, BECAUSE
PROCESSOR DID NOT READ
PREVIOUS DATA, OVERRUN
BIT SET IN STATUS REGISTER
B
B
N
N
B
N
P
P
P
Stop
Stop
Stop Start
Start
Start
B
B
0
0
B
CHAR # n+3
B
0
1
B
N
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