w65c51n Western Design Center, Inc., w65c51n Datasheet - Page 12

• Manufacturer Part Number: w65c51n
• Description: Asynchronous Communications Interface Adapter Acia
• Manufacturer: Western Design Center, Inc.

INTERFACE SIGNALS
Figure 4 shows the ACIA interface signals associated with the microprocessor and the modem.
MICROPROCESSOR INTERFACE
Reset (RESB)
During System initialization a low on the RESB input causes a hardware reset to occur. Upon reset, the
Command Register and the Control Register are cleared (all bits set to 0). The Status Register is cleared
with the exception of the indications of Data Set Ready and Data Carrier Detect, which are externally
controlled by the DSRB and DCDB lines, and the transmitter Empty bit, which is set. RESB must be held
low for one PHI2 clock cycle for a reset to occur.
Input Clock (PHI2)
The input clock is the system PHI2 clock and clocks all data transfers between the system
microprocessor and the ACIA.
Read/Write (RWB)
The RWB input, generated by the microprocessor controls the direction of data transfers. A high on the
RWB pin allows the processor to read the data supplied by the ACIA, a low allows a write to the ACIA.
Interrupt Request (IRQB)
D0-D7
RESB
VCC
VSS
IRQB
RWB
CS0
CS1B
RS0
RS1
Ø2
DATA BUS
BUFFERS
TIMING &
CONTROL
LOGIC
INTERRUPT
LOGIC
I/O
CONTROL
TRANSMIT
CONTROL
TRANSMIT
DATA &
SHIFT
REGISTERS
BAUD RATE
GENERATOR
CONTROL
REGISTER
COMMAND
REGISTER
RECEIVE
DATA &
SHIFT
REGISTERS
STATUS
REGISTER
RECEIVE
CONTROL
Figure 4 ACIA Interface Diagram
RxD
CTSB
TxD
XTLI
XTLO
DTRB
RTSB
DCDB
DSRB
RxC
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