w65c51n Western Design Center, Inc., w65c51n Datasheet - Page 7

• Manufacturer Part Number: w65c51n
• Description: Asynchronous Communications Interface Adapter Acia
• Manufacturer: Western Design Center, Inc.

STATUS REGISTER BIT DESCRIPTION
Parity error (Bit 0) Framing Error (Bit 1) and Overrun (Bit 2)
None of these bits causes a processor interrupt to occur but, they are normally checked at the time the
Receiver Data Register is read so that the validity of the data can be verified. These bits are self clearing
(i.e., they are automatically cleared after a read of the Receiver Data Register).
Receiver Data Register Full (Bit 3)
This bit goes to a 1 when the ACIA transfers data from the Receiver Shift Register to the Receiver Data
Register and goes to a 0 (is cleared) when the processor reads the Receiver Data Register.
Transmitter Data Register Empty (Bit 4)
This bit goes to a 1 when the ACIA transfers data from the Transmitter Data Register to the Transmitter
Shift Register and goes to a 0 (is cleared) when the processor writes new data onto the Transmitter Data
Register.
Data Carrier Detect (Bit 5) and Data Set Ready (Bit 6)
These bits reflect the levels of the DCDB and DSRB inputs to the ACIA. A 0 indicates a low level (true
condition) and a 1 indicates a high level (false). Whenever either of these inputs change state, an
immediate processor interrupt (IRQ) occurs, unless bit 1 of the Command Register (IRD) is set to a 1 to
disable IRQB. When the interrupt occurs, the status bits indicate the levels of the inputs immediately after
the change of state occurred. Subsequent level changes will not affect the status bits until the Status
Register is interrogated by the processor. At that time, another interrupt will immediately occur and the
status bits reflect the new input levels. These bits are not automatically cleared (or reset) by an internal
operation.
Interrupt (Bit 7)
This bit goes to a 1 whenever an interrupt condition occurs and goes to a 0 (is cleared) when the Status
Register is read.
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