w65c51n Western Design Center, Inc., w65c51n Datasheet - Page 22

• Manufacturer Part Number: w65c51n
• Description: Asynchronous Communications Interface Adapter Acia
• Manufacturer: Western Design Center, Inc.

STATUS REGISTER OPERATION
Because of the special functions of the various status bits, there is a suggested sequence for checking
them. When an interrupt occurs, the ACIA should be interrogated as follows:
1. Read Status Register
This operation automatically clears Bit 7 (IRQB). Subsequent transitions on DSRB and DCDB will cause
another interrupt.
2. Check IRQB (Bit 7) in the data read from the Status Register.
If not set, the interrupt source is not the ACIA.
3. Check DCDB and DSRB
These must be compared to their previous levels, which must have been saved by the processor. If they
are both 0 (modem “on-line”) and they are unchanged then the remaining bits must be checked.
4. Check RDRF (Bit 3)
Check for Receiver Data Register Full.
5. Check Parity, Overrun and Framing Error (Bits 0-2) if the Receiver Data Register is full.
6. Check TDRE (Bit 4)
Check for Transmitter Data Register Empty.
7. If none of the above conditions exist, then CTSB must have gone to the false (high) state.
PROGRAM RESET OPERATION
A program reset occurs when the processor performs a write operation to the ACIA with RS0 low and
RS1 high. The program reset operates somewhat different from the hardware reset (RESB pin) and is
described as follows:
1. Internal registers are not completely cleared. Check register formats for the effect of a program reset
on internal registers
2. The DTRB line goes high immediately.
3 Receiver and transmitter interrupts are disabled immediately. If IRQB is low when the reset occurs, it
stays low until serviced, unless interrupt was caused by DCDB or DSRB transition.
4. DCDB and DSRB interrupts are disabled immediately. If IRQB is low and was caused by DCDB or
DSRB, then it goes high, also DCDB and DSRB status bits subsequently will follow the input lines,
although no interrupt will occur.
5. Overrun cleared, if set.
MISCELLANEOUS
1. If Echo Mode is selected, RTSB goes low.
2. If Bit 0 of Command Register is 0 (disabled) then:
3. Odd parity occurs when the sum of all the 1 bits in the data word (including the parity bit) is odd.
4. In the receive mode, the received parity bit does not go into the Receiver Data Register, but generates
parity error or no parity error for the Status Register.
5. Transmitter and Receiver may be in full operation simultaneously. This is “full-duplex” mode.
6. If the RxD line inadvertently goes low and then high right after a Stop Bit, the ACIA does not interpret
this as a Start Bit, but samples the line again halfway into the bit to determine if it is a true Start Bit or a
false one. For false Start Bit detection, the ACIA does not begin to receive data, instead, only a true Start
Bit initiates receiver operation.
a) All interrupts are disabled including those caused by DCDB and DSRB transitions.
b) Transmitter is disabled immediately.
c) Receiver is disabled, but a character currently being received will be completed first.
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