w65c51n Western Design Center, Inc., w65c51n Datasheet - Page 19

• Manufacturer Part Number: w65c51n
• Description: Asynchronous Communications Interface Adapter Acia
• Manufacturer: Western Design Center, Inc.

Overrun in Echo Mode
If Overrun occurs in Echo Mode, the Receiver is affected the same way as a normal overrun in Receive
Mode. For the retransmitted data, when overrun occurs, the TxD line goes to the “MARK” condition until
the first Start Bit after the Receiver Data Register is read by the processor. Figure 12 shows the timing
relationship for this mode.
Framing Error
Framing Error is caused by the absence of Stop Bit(s) on received data. A Framing Error is indicated by
the setting of bit 1 in the Status Register at the same time the Receiver Data Register Full bit is set, also
in the Status Register. In response to IRQB, generated by RDRF, the Status Register can also be
checked for the Framing Error. Subsequent data words are tested for Framing Error separately, so the
status bit will always reflect the last data word received.
relationship.
PROCESSOR
INTERRUPT FOR
RECEIVER DATA
REGISTER FULL
IRQB
RxD
TxD
P
Stop
Stop Start
Start
PROCESSOR
READS STATUS
REGISTER
B
0
B
RxD
(EXPECTED)
RxD
(ACTUAL)
0
CHAR # n
PROCESSOR DOES
NOT READ
RECEIVER DATA
REGISTER
B
1
B
NOTES: 1. FRAMING ERROR DOES NOT
1
IRQB
B
2. IF NEXT DATA WORD IS OK,
N
B
INHIBIT RECEIVER OPERATION
FRAMING ERROR IS CLEARED
OVERRUN OCCURS
TxD GOES TO
“MARK”
CONDITION
N
P
B
B
P
Stop
6
6
P
P
Figure 12 Overrun in Echo Mode
Start
Stop
Stop
1
1
B
0
Stop
Stop
Figure 13 Framing Error
2
2
B
1
Start
Start
B
B
0
0
B
N
B
B
1
1
P
B
B
PROCESSOR FINALLY
READS RECEIVER
DATA REGISTER,
LAST VALID
CHARACTER (#n)
2
2
Stop
B
B
Start
3
3
B
B
4
4
B
See Figure 13 for Framing Error timing
0
MISSING
STOP BIT
B
B
CHAR # x
5
5
B
1
B
B
6
6
P
P
B
N
Stop
Stop
1
1
PROCESSOR
INTERRUPT,
FRAMING
ERROR
BIT SET
P
Stop
Stop
2
2
PROCESSOR
INTERRUPT FOR
CHAR#x IN
RECEIVER DATA
REGISTER
Stop
Start
Start
TxD DATA
RESUMES
Start
Start
B
B
0
0
B
0
B
CHAR # x+1
0
B
1
B
1
B
N
B
N
P
P
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