SDA9410-B13 MICRONAS [Micronas], SDA9410-B13 Datasheet - Page 117

• Manufacturer Part Number: SDA9410-B13
• Description: Display Processor and Scan Rate Converter using Embedded DRAM Technology Units
• Manufacturer: MICRONAS [Micronas]

SDA9410
5.13
5.13.1
Write Address: BCh
Read Address: BDh
5.13.2
The SDA 9410 I
provides two different access modes (write, read). All modes run with a sub address auto
increment. The interface supports the normal 100 kHz transmission speed as well as the
high speed 400 kHz transmission.
write:
S: Start condition
A: Acknowledge
P: Stop condition
NA: Not Acknowledge
read:
The transmitted data are internally stored in registers. The master has to write a don’t
care byte to the sub address FFh (store command) to make the register values available
for the SDA 9410. To have a defined time step, where the data will be available, the data
are made valid with the incoming V-sync VINM or VINS or with the next OPSTARTM
pulse, which is an internal signal and indicates the start of a new output cycle. The sub
addresses, where the data are made valid with the VINM signal are indicated in the
overview of the sub addresses with „VIM“, where the data are made valid with the VINS
are indicated with “VIS” and where the data are made valid with the OPSTARTM are
indicated with „OS“. The I²C parameter VIMSTATUS, VISSTATUS and OSSTATUS (sub
address 80h, 81h, 82h) reflect the state of the register values. If these bits are read as
117
S 1 0 1 1 1 1 0 0 A Sub address A Data Byte
S 1 0 1 1 1 1 0 0 A Sub address A S 1 0 1 1 1 1 0 1 A
Data Byte
I²C Bus
I²C Bus slave address
I²C Bus format
²
C Bus interface acts as a slave receiver and a slave transmitter and
A Data Byte
1 0 1 1 1 1 0 0
1 0 1 1 1 1 0 1
NA
P
A *****
Preliminary Data Sheet
A
Micronas
I²C Bus
P