SDA9410-B13 MICRONAS [Micronas], SDA9410-B13 Datasheet - Page 158

• Manufacturer Part Number: SDA9410-B13
• Description: Display Processor and Scan Rate Converter using Embedded DRAM Technology Units
• Manufacturer: MICRONAS [Micronas]

SDA9410
158
Sub address 53
Bit
D2
D1
D0
Sub address 54
Bit
D7...D0
Sub address 55
Bit
D7
D6
Name
SLAVEON Reading Data of Slave Channel
MEMRDM Memory Read Mode Master Channel (SRC-Mode)
MEMRDS
Name
VPAN
Name
REFRON
RSHFTM
Function
1: enabled (slave picture is displayed)
0: disabled
1:reading only 1 field memory area for AABB conversion
0:reading both field memory areas for ABAB conversion
Memory Read Mode Slave Channel (SRC-Mode)
1:reading data in SSC-configuration, 1 or 2 decimated fields,
AABB
0:reading data in PIP-configuration (joint line free, ABAB)
Function
Vertical Panning
-line number indicating the start line of reading for the master
channel
-defines the displayed part of the picture with activated vertical
interpolation
[VPAN=0]
Function
Refresh On
1: memory refresh activated
0: no memory refresh
Joint Line Free Display of Master Channel by Shifting the
Output Raster Phase (SSC-Mode): Should be set in all
operation modes to 1
1: enabled
0: disabled
Preliminary Data Sheet
Micronas
I²C Bus