SDA9410-B13 MICRONAS [Micronas], SDA9410-B13 Datasheet - Page 40
SDA9410-B13
Manufacturer Part Number
SDA9410-B13
Description
Display Processor and Scan Rate Converter using Embedded DRAM Technology Units
Manufacturer
MICRONAS [Micronas]
Datasheet
1.SDA9410-B13.pdf
(179 pages)
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SDA9410
5.4.3
The figure below shows a block diagram of the spatial and temporal motion adaptive
noise reduction (first order IIR filter). The spatial noise reduction is only performed on the
luminance signal. The structure of the temporal motion adaptive noise reduction is the
same for the luminance as for the chrominance signal.
Figure 15
5.4.3.1
Normally a spatial noise reduction reduces the resolution due to the low pass
characteristic of the used filter. Therefore the spatial noise reduction of the SDA 9410
works adaptive on the picture content. The low pas filter process is only executed on a
homogeneous area.
Table 21
40
I²C Bus parameter
SNRON
1: on
0: off
TNRHOC,
TNRKOC,
TNRCLC,
TNRVAC,
TNRHOY,
TNRKOY,
TNRVAY,
TNRFIC,
TNRCLY,
TNRFIY,
NRON
NRON
UVIN
YIN
Noise reduction
Spatial noise reduction
Block diagram of noise reduction
Input write I²C Bus parameter
reduction
SNRON
Spatial
noise
Sub address
1Ah
YSNR
UVSNR
DUV
DY
detector
detector
Motion
Motion
YR
UV1
KY
KUV
1
0
Description
Spatial noise reduction of luminance signal
TNRSEL
Frame
delay
delay
Frame
Field
delay
delay
Field
1
0
0
1
Input signal processing
DTNRON
DTNRON
Preliminary Data Sheet
UVOUT
YOUT
Micronas
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