SDA9410-B13 MICRONAS [Micronas], SDA9410-B13 Datasheet - Page 28

• Manufacturer Part Number: SDA9410-B13
• Description: Display Processor and Scan Rate Converter using Embedded DRAM Technology Units
• Manufacturer: MICRONAS [Micronas]

SDA9410
The Figure 9 shows the generation of the internal H- and V-syncs in case of full CCIR
656 mode. The H656 sync is generated after the EAV. The V656 and F656 signals
change synchronously with the EAV timing reference code.
Figure 9
The Figure 10 explains the functionality of the SYNCENM/SYNCENS signal. The SDA
9410 needs the SYNCENM/SYNCENS (synchronization enable) signal, which is used to
gate the YINM/YINS, UVINM/UVINS as well as the HINM/HINS and the VINM/VINS
signal. This is implemented for frontends which are working with 13.5 MHz and a large
output delay time for YINM/YINS, UVINM/UVINS, HINM/HINS and VINM/VINS (e.g.
Micronas VPC32XX, output delay: 35 ns). For this application the half system clock
CLKM/CLKS (13.5 MHz) from the frontend should be provided at this pin. In case the
frontend is working at 27.0 MHz with sync signals having delay times smaller than 25 ns,
this input can be set to low level (SYNCENM/SYNCENS= V
output delay: 25 ns). Thus the signals YINM/YINS, UVINM/UVINS, HINM/HINS and
VINM/VINS are sampled with the CLKM/CLKS system clock when the SYNCENM/
SYNCENS input is low.
The Figure 10 shows the gated inputs signals YINMen, UVINMen, HINMen and
VINMen.
28
CLK1 (27 MHz)
CLK1 (27 MHz)
YIN
YIN
H656
CCIR 656 interface
V656
(e.g.)
F656
(e.g.)
MSB
Explanation of 656 format
x
11111111
11111111
LSB
EAV
EAV
00000000
00000000
1716 Tclk1(NTSC)
276 Tclk1(NTSC)
1728 Tclk1(PAL)
288 Tclk1(PAL)
EAV
SAV
x
00000000
00000000
x
SAV
1FV1P
1FV0P
Input format conversion (IFCM/IFCS)
SAV
3
3
P
P
2
2
P
P
1
1
P
P
0
0
u0
x
y0
V = 1 during field blanking
SS
F = 0 during field 1(A)
F = 1 during field 2(B)
) (e.g. Micronas SDA 9206,
v0
V = 0 elsewhere
x
y1
Preliminary Data Sheet
u2
EAV
y3
Micronas
x
EAV