SDA9410-B13 MICRONAS [Micronas], SDA9410-B13 Datasheet - Page 51

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SDA9410-B13

Manufacturer Part Number
SDA9410-B13
Description
Display Processor and Scan Rate Converter using Embedded DRAM Technology Units
Manufacturer
MICRONAS [Micronas]
Datasheet
SDA9410
5.5
Table 33
Table 34
The SDA 9410 supports different clock concepts. The Figure 24 shows a typical
application of the SDA 9410. The frontend clock is connected to CLKM input. The
second frontend clock is connected to CLKS input. The CLKOUT pin is connected to the
backend and the X1/CLKD input is connected to a crystal oscillator. The Figure 23
explains the clock switch, which may be used for the separate modes (see also Table
37 "Ingenious configurations of the HOUT and VOUT generator" on page 80).
Figure 23
51
Signals
CLKM
CLKS
X1/CLKD
Clock concept
Input signals
Output signals
Clock concept of SDA 9410
X1/CLKD
Pin number
18
58
2
CLKM
CLKS
Signals
CLKOUT
CLKMDEN
0
1
Description
System clock input master channel
System clock input slave channel
System clock input display channel
Pin number
3
PLLS
PLLM
PLLD
CLKS_pll
CLKM_pll
CLKD_pll
Description
Clock output
CLKOUT
Preliminary Data Sheet
Clock concept
Micronas

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