SDA9410-B13 MICRONAS [Micronas], SDA9410-B13 Datasheet - Page 55

• Manufacturer Part Number: SDA9410-B13
• Description: Display Processor and Scan Rate Converter using Embedded DRAM Technology Units
• Manufacturer: MICRONAS [Micronas]

SDA9410
Figure 25
Additionally 3 fields of a decimated picture of the slave channel with the size of up to 1/
9 of the original format can be stored (4:1:1 or 4:2:0 format). In this mode motion
estimation and compensation (Micronas VDU algorithm) for the master channel is
supported (up to 30 MHz clock frequency). In parallel it is possible to insert the slave
channel at any display position using frame mode and without joint lines. Noise reduction
algorithm by recursive filtering is supported only for the master channel in SRC-Mode.
In SSC-Mode the data configuration of master and slave channel can be different.
Depending on the picture size it is possible to store only 1 field of luminance and
chrominance data or 2 fields. The data configuration can be defined by the I²C Bus
parameters ORGMEMM and ORGMEMS, respectively.
Table 39
Table 40
55
ORGMEMS
1
0
ORGMEMM
1
0
2. line
1. line
3. line
Y0
Y0
Y0
Supported data formats
Definition of ORGMEM
Definition of ORGMEMS
U0
U0
V0
V0
U0
V0
Y1
Y1
Y1
Data configuration of the memory
3 fields PIP (SRC-Mode),
2 fields (restricted picture size, SSC and MUP Mode)
Slave channel blocked (SRC-Mode and ORGMEMM=1)
1 field (SSC- and MUP-Mode; SRC-Mode and ORGMEMM=0)
Data configuration of the memory
2 fields (limited picture size in SSC- and MUP-Mode)
1 field
4:2:2
Y2
Y2
Y2
U2
V2
U2
V2
U2
V2
Y3
Y3
Y3
Y4
Y4
Y4
U4
U4
V4
V4
U4
V4
Y5
Y5
Y5
Y6
Y6
Y6
U6
V6
U6
V6
U6
V6
Y7
Y7
Y7
Y0
Y0
Y0
Y1
Y1
Y1
U0
V0
U0
V0
U0
V0
4:1:1
Y2
Y2
Y2
Application modes and memory concept
Y3
Y3
Y3
Y4
Y4
Y4
Y5
Y5
Y5
U4
V4
U4
V4
U4
V4
Y6
Y6
Y6
Y7
Y7
Y7
Y0
Y0
Y0
U0
V0
U0
V0
Y1
Y1
Y1
4:2:0
Y2
Y2
Y2
Preliminary Data Sheet
U2
V2
U2
V2
Y3
Y3
Y3
Y4
Y4
Y4
U4
V4
U4
V4
Y5
Y5
Y5
Y6
Y6
Y6
U6
V6
U6
V6
Y7
Y7
Y7
Micronas