S29CD-J_12 SPANSION [SPANSION], S29CD-J_12 Datasheet - Page 75

• Manufacturer Part Number: S29CD-J_12
• Manufacturer: SPANSION [SPANSION]

20. Appendix 2
20.1
Legend
BA = Bank Address. The set of addresses that comprise a bank. The system may
write any address within a bank to identify that bank for a command.
PA = Program Address (Amax–A0). Addresses latch on the falling edge of the
WE# or CE# pulse, whichever happens later.
PD = Program Data (DQmax–DQ0) written to location PA. Data latches on the
rising edge of WE# or CE# pulse, whichever happens first.
Notes
1. See
2. All values are in hexadecimal.
3. Shaded cells in table denote read cycles. All other cycles are write
4. During unlock cycles, (lower address bits are 555 or 2AAh as shown in table)
5. No unlock or command cycles required when bank is reading array data.
6. The Reset command is required to return to the read mode (or to the erase-
7. The fourth cycle of the autoselect command sequence is a read cycle. The
October 11, 2012 S29CD-J_CL-J_00_B7
Read (5)
Reset (6)
Autoselect
(7)
Program
Chip Erase
Sector Erase
Program/Erase Suspend (9)
Program/Erase Resume (10)
CFI Query (11, 12)
Accelerated Program (13)
Configuration Register Verify (12)
Configuration Register Write (14)
Unlock Bypass Entry (15)
Unlock Bypass Program (15)
Unlock Bypass Erase (15)
Unlock Bypass CFI (11, 15)
Unlock Bypass Reset (15)
operations.
address bits higher than A11 (except where BA is required) and data bits
higher than DQ7 are don’t cares.
suspend-read mode if previously in Erase Suspend) when a bank is in the
autoselect mode, or if DQ5 goes high (while the bank is providing status
information).
system must provide the bank address to obtain the manufacturer ID or
device ID information. See
Table 8.1
Command (Notes)
Command Definitions
Manufacturer ID
Device ID (8)
for description of bus operations.
Autoselect on page 30
1
1
4
6
4
6
6
1
1
1
2
3
4
3
2
2
1
2
Table 20.1 Memory Array Command Definitions (x32 Mode)
Addr
XXX
555
555
555
555
555
555
555
555
RA
BA
BA
XX
XX
XX
XX
XX
55
First
Data
for more information.
RD
AA
AA
AA
AA
AA
B0
A0
AA
AA
AA
A0
F0
30
98
80
98
90
D a t a
S29CD-J and S29CL-J Flash Family
Addr
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
XX
XX
PA
PA
Second
S h e e t
Data
PD
PD
55
55
55
55
55
55
55
55
10
00
BA+555
Addr
RA = Read Address (Amax–A0).
RD = Read Data. Data DQmax–DQ0 at address location RA.
SA = Sector Address. The set of addresses that comprise a sector. The system
may write any address within a sector to identify that sector for a command.
WD = Write Data. See “Configuration Register” definition for specific write data.
Data latched on rising edge of WE#.
X = Don’t care
8. The device ID must be read across the fourth, fifth, and sixth cycles. 00h in
9. The system may read and program in non-erasing sectors when in the
10. The Program/Erase Resume command is valid only during the Erase
11. Command is valid when device is ready to read array data.
12. Asynchronous read operations.
13. ACC must be at V
14. Command is ignored during any Embedded Program, Embedded Erase, or
15. The Unlock Bypass Entry command is required prior to any Unlock Bypass
555
555
555
555
555
555
555
the sixth cycle indicates ordering option 00, 01h indicates ordering option 01.
Program/Erase Suspend mode. The Program/Erase Suspend command is
valid only during a sector erase operation, and requires the bank address.
Suspend mode, and requires the bank address.
Suspend operation.
operation. The Unlock Bypass Reset command is required to return to the
read mode.
Third
Bus Cycles (Notes 1–4)
Data
A0
C6
D0
90
90
80
80
20
BA+X00
BA+X01
BA+XX
Addr
ID
555
555
XX
PA
during the entire operation of this command.
Fourth
Data
WD
PD
AA
AA
RD
01
7E
BA+X0E
Addr
2AA
2AA
Fifth
Data
09
55
55
BA+X0F
Addr
555
SA
Sixth
00/01
Data
10
30
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