S29CD-J_12 SPANSION [SPANSION], S29CD-J_12 Datasheet - Page 42

• Manufacturer Part Number: S29CD-J_12
• Manufacturer: SPANSION [SPANSION]

42
8.8.6
8.8.7
DQ3: Sector Erase Timer
RY/BY#: Ready/Busy#
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not
erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors
are selected for erasure, the entire time-out also applies after each additional sector erase command. When
the time-out period is complete, DQ3 switches from a “0” to a “1.” If the time between additional sector erase
commands from the system can be assumed to be less than 50 µs, the system need not monitor DQ3. See
Sector Erase on page 33
After the sector erase command is written, the system reads the status of DQ7 (Data# Polling) or DQ6
(Toggle Bit I) to ensure that the device has accepted the command sequence, then reads DQ3. If DQ3 is “1,”
the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until
the erase operation is complete. If DQ3 is “0,” the device accepts additional sector erase commands.
To ensure the command has been accepted, the system software check the status of DQ3 prior to and
following each sub-sequent sector erase command. If DQ3 is high on the second status check, the last
command might not have been accepted.
The device provides a RY/BY# open drain output pin as a way to indicate to the host system that the
Embedded Algorithms are either in progress or have been completed. If the output of RY/BY# is low, the
device is busy with either a program, erase, or reset operation. If the output is floating, the device is ready to
accept any read/write or erase operation. When the RY/BY# pin is low, the device will not accept any
additional program or erase commands with the exception of the Erase suspend command. If the device has
entered Erase Suspend mode, the RY/BY# output is floating. For programming, the RY/BY# is valid (RY/BY#
= 0) after the rising edge of the fourth WE# pulse in the four write pulse sequence. For chip erase, the RY/
BY# is valid after the rising edge of the sixth WE# pulse in the six write pulse sequence. For sector erase, the
RY/BY# is also valid after the rising edge of the sixth WE# pulse.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a 0 (busy) until the
internal reset operation is complete, which requires a time of t
system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is
asserted when a program or erase operation is not executing (RY/BY# pin is floating), the reset operation is
completed in a time of t
RESET# pin returns to V
Since the RY/BY# pin is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-
up resistor to V
open drain.
Table 8.9
Figure 18.8
Notes
1. DQ5 switches to 1 when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See
2. DQ7 and DQ2 require a valid address when reading status information. See
Exceeded Timing Limits on page 41
on page 39
Standard
Suspend
Mode
Erase
Mode
shows the outputs for RY/BY#, DQ7, DQ6, DQ5, DQ3 and DQ2.
for further details.
and
CC
Figure 18.9
Embedded Program Algorithm
Embedded Erase Algorithm
Reading within Erase
Suspended Sector
Reading within Non-Erase
Suspended Sector
Erase-Suspend-Program
. An external pull-up resistor is required to take RY/BY# to a V
Operation
READY
IH
for more details.
.
S29CD-J and S29CL-J Flash Family
show RY/BY# for read, reset, program, and erase operations, respectively.
(not during Embedded Algorithms). The system can read data t
for more information.
Table 8.9 Write Operation Status
Table 8.9
D a t a
(Note 2)
DQ7#
DQ7#
DQ7
Data
0
1
shows the status of DQ3 relative to the other status bits.
S h e e t
No toggle
Toggle
Toggle
Toggle
DQ6
Data
READY
DQ7: Data# Polling on page 37
(during Embedded Algorithms). The
S29CD-J_CL-J_00_B7 October 11, 2012
(Note 1)
DQ5
Data
0
0
0
0
Figure
IH
DQ3
Data
N/A
N/A
N/A
level since the output is an
18.2,
1
and
Figure
No toggle
(Note 2)
Toggle
Toggle
DQ2
Data
N/A
DQ2: Toggle Bit II
RH
18.6,
after the
RY/BY#
DQ5:
0
0
1
1
0