S29CD-J_12 SPANSION [SPANSION], S29CD-J_12 Datasheet - Page 49

• Manufacturer Part Number: S29CD-J_12
• Manufacturer: SPANSION [SPANSION]

9.6
October 11, 2012 S29CD-J_CL-J_00_B7
9.6.1
9.6.2
9.6.3
9.6.4
9.6.5
9.6.6
Hardware Data Protection Methods
WP# Method
Low V
Write Pulse “Glitch Protection”
Power-Up Write Inhibit
V
Logical Inhibit
The device offers several methods of data protection by which intended or accidental erasure of any sectors
can be prevented via hardware means. The following subsections describe these methods.
The Write Protect feature provides a hardware method of protecting the two outermost sectors of the large
bank.
If the system asserts V
“outermost” boot sectors (8-Kbyte sectors) in the large bank. If the system asserts V
device reverts to whether the boot sectors were last set to be protected or unprotected. That is, sector
protection or unprotection for these sectors depends on whether they were last protected or unprotected.
Note that the WP# pin must not be left floating or unconnected as inconsistent behavior of the device may
result.
The WP# pin must be held stable during a command sequence execution
When V
power-up and power-down.
The command register and all internal program/erase circuits are disabled, and the device resets to reading
array data. Subsequent writes are ignored until V
proper signals to the control inputs to prevent unintentional writes when V
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
If WE# = CE# = RESET# = V
rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up.
The device imposes no restrictions on V
to V
operating voltages. Once V
permitted. Refer to timing in
Write cycles are inhibited by holding any one of OE# = V
CE# and WE# must be a logical zero (V
CC
IL
and V
is required during the entire V
CC
CC
Write Inhibit
is less than V
IO
Power-up And Power-down Sequencing
IL
LKO
on the WP# pin, the device disables program and erase functions in the two
D a t a
CC
S29CD-J and S29CL-J Flash Family
, the device does not accept any write cycles. This protects data during V
V
IL
CC
and V
and OE# = V
and V
S h e e t
CC
IO
and V
attain the operating voltages, deassertion of RESET# to V
IO
CC
IL
) while OE# is a logical one (V
Power-up on page
and V
IH
IO
during power-up, the device does not accept commands on the
power sequence until the respective supplies reach the
IO
CC
power-up or power-down sequencing. Asserting RESET#
is greater than V
IL
, CE# = V
57.
IH
LKO
, or WE# = V
IH
. The system must provide the
).
CC
is greater than V
IH
. To initiate a write cycle,
IH
on the WP# pin, the
LKO
.
IH
is
CC
49