S29CD-J_12 SPANSION [SPANSION], S29CD-J_12 Datasheet - Page 29

• Manufacturer Part Number: S29CD-J_12
• Manufacturer: SPANSION [SPANSION]

Notes
1. Burst access starts with a rising CLK edge and when ADV# is active.
2. Configurations register 6 is always set to 1 (CR6 = 1). Burst starts and data outputs on the rising CLK edge.
3. CR [13-10] = 1 or three clock cycles.
4. CR [13-10] = 2 or four clock cycles.
5. CR [13-10] = 3 or five clock cycles.
October 11, 2012 S29CD-J_CL-J_00_B7
DQ31-DQ0
DQ31-DQ0
DQ31-DQ0
Addresses
8.4.3
ADV#
CLK
3
4
5
Configuration Register
The configuration register sets various operational parameters associated with burst mode. Upon power-up
or hardware reset, the device defaults to the asynchronous read mode and the configuration register settings
are in their default state. (See
determines the proper settings for the entire configuration register, and then execute the Set Configuration
Register command sequence before attempting burst operations. The configuration register is not reset after
deasserting CE#.
The Configuration Register does not occupy any addressable memory location, but rather, is accessed by the
Configuration Register commands. The Configuration Register is readable at any time, however, writing the
Configuration Register is restricted to times when the Embedded Algorithm™ is not active. If the user
attempts to write the Configuration Register while the Embedded Algorithm is active, the write operation is
ignored and the contents of the Configuration Register remain unchanged.
The Configuration Register is a 16 bit data field which is accessed by DQ15–DQ0. During a read operation,
DQ31–DQ16 returns all zeroes. Also, the Configuration Register reads operate the same as the Autoselect
command reads. When the command is issued, the bank address is latched along with the command. Read
operations to the bank that was specified during the Configuration Register read command return
Configuration Register contents. Read operations to the other bank return flash memory data. Either bank
address is permitted when writing the Configuration Register read command.
The configuration register can be read with a four-cycle command sequence. See
on page 75
Table 8.5
Valid Address
describes the Configuration Register settings.
1st CLK
for sequence details.
Address 1 Latched
Three CLK Delay
2nd CLK
D a t a
Four CLK Delay
Five CLK Delay
S29CD-J and S29CL-J Flash Family
Table 8.6
S h e e t
Figure 8.4 Initial Burst Delay Control
3rd CLK
for the default Configuration Register settings.) The host system
D0
4th CLK
D1
D0
5th CLK
D2
D1
D0
Command Definitions
D2
D3
D1
D2
D4
D3
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