S29CD-J_12 SPANSION [SPANSION], S29CD-J_12 Datasheet - Page 30

• Manufacturer Part Number: S29CD-J_12
• Manufacturer: SPANSION [SPANSION]

8.5
30
Autoselect
The autoselect mode provides manufacturer and device identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to
automatically match a device to be programmed with its corresponding programming algorithm. However, the
autoselect codes can also be accessed in-system through the command register.
When using programming equipment, the autoselect mode requires V
A1, and A0 must be as shown in
Configuration Register
CR15 = Read Mode (RM)
0 = Synchronous Burst Reads Enabled
1 = Asynchronous Reads Enabled (Default)
CR14 = Reserved for Future Enhancements
These bits are reserved for future use. Set these bits to 0.
CR13–CR10 = Initial Burst Access Delay Configuration (IAD3-IAD0)
0000 = 2 CLK cycle initial burst access delay
0001 = 3 CLK cycle initial burst access delay
0010 = 4 CLK cycle initial burst access delay
0011 = 5 CLK cycle initial burst access delay
CR9 = Data Output Configuration (DOC)
0 = Hold Data for 1-CLK cycle—Default
1 = Reserved
CR8 = IND/WAIT# Configuration (WC)
0 = IND/WAIT# Asserted During Delay—Default
1 = IND/WAIT# Asserted One Data Cycle Before Delay
CR7 = Burst Sequence (BS)
0 = Reserved
1 = Linear Burst Order—Default
CR6 = Clock Configuration (CC)
0 = Reserved
1 = Burst Starts and Data Output on Rising Clock Edge—Default
CR5–CR3 = Reserved For Future Enhancements (R)
These bits are reserved for future use. Set these bits to 0.
CR2–CR0 = Burst Length (BL2–BL0)
000 = Reserved, burst accesses disabled (asynchronous reads only)
001 = 64 bit (8-byte) Burst Data Transfer - x32 Linear
010 = 128 bit (16-byte) Burst Data Transfer - x32 Linear
011 = 256 bit (32-byte) Burst Data Transfer - x32 Linear (device default)
100 = Reserved, burst accesses disabled (asynchronous reads only)
101 = Reserved, burst accesses disabled (asynchronous reads only)
110 = Reserved, burst accesses disabled (asynchronous reads only)
CR15
CR7
RM
BS
1
1
Reserve
CR14
CR6
CC
0
1
Table 8.6 Configuration Register After Device Reset
S29CD-J and S29CL-J Flash Family
Reserve
CR13
IAD3
CR5
0
0
Table
Table 8.5 Configuration Register
8.7. In addition, when verifying sector protection, the sector address
D a t a
Reserve
CR12
IAD2
CR4
1
0
0100 = 6 CLK cycle initial burst access delay
0101 = 7 CLK cycle initial burst access delay
0110 = 8 CLK cycle initial burst access delay
0111 = 9 CLK cycle initial burst access delay—Default
S h e e t
Reserve
CR11
IAD1
CR3
1
0
ID
S29CD-J_CL-J_00_B7 October 11, 2012
on address pin A9. Ad-dress pins A6,
CR10
IAD0
CR2
BL2
1
1
DOC
CR9
CR1
BL1
0
0
Reserve
CR8
CR0
BL0
0
0