S29CD-J_12 SPANSION [SPANSION], S29CD-J_12 Datasheet - Page 71
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S29CD-J_12
Manufacturer Part Number
S29CD-J_12
Description
Manufacturer
SPANSION [SPANSION]
Datasheet
1.S29CD-J_12.pdf
(81 pages)
- Current page: 71 of 81
- Download datasheet (4Mb)
18.8
Notes
1. Typical program and erase times assume the following conditions: 25°C, 2.5V V
2. Under worst case conditions of 145°C, V
3. The typical chip programming time is considerably less than the maximum chip programming time listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See
6. PPBs have a program/erase cycle endurance of 100 cycles.
7. Guaranteed cycles per sector is 100K minimum.
18.9
October 11, 2012 S29CD-J_CL-J_00_B7
Sector Erase Time
Chip Erase Time
Double Word Program Time
Accelerated Double Word Program Time
Accelerated Chip Program Time
Chip Program Time, x32
pattern.
information on command definitions.
Erase and Programming Performance
PQFP and Fortified BGA Pin Capacitance
Parameter
Notes
1. Sampled, not 100% tested.
2. Test conditions T
(Note 3)
Parameter Symbol
C
C
C
OUT
IN2
IN
A
CC
= 25°C, f = 1.0 MHz.
= 2.5V, 1M cycles.
Table 18.7 Erase and Programming Performance
D a t a
16 Mb = 23
32 Mb = 46
32 Mb = 10
16 Mb = 12
32 Mb = 24
16 Mb = 5
(Note 1)
Table 18.8 PQFP and Fortified BGA Pin Capacitance
S29CD-J and S29CL-J Flash Family
Typ
0.5
8
8
S h e e t
Control Pin Capacitance
Parameter Description
Output Capacitance
Input Capacitance
16 Mb = 230
32 Mb = 460
32 Mb = 100
16 Mb = 120
32 Mb = 240
16 Mb = 50
(Note 2)
Max
130
130
CC
5
, 100K cycles. Additionally, programming typicals assume checkerboard
Unit
µs
µs
s
s
s
s
Excludes 00h programming prior to erasure
(Note 4)
Excludes system level overhead
Test Setup
V
V
V
OUT
IN
IN
= 0
= 0
= 0
Table 20.1
Comments
Typ
8.5
7.5
6
and
Table 20.2
(Note 5)
Max
7.5
12
9
for further
Unit
pF
pF
pF
71
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