S29CD-J_12 SPANSION [SPANSION], S29CD-J_12 Datasheet - Page 26

• Manufacturer Part Number: S29CD-J_12
• Manufacturer: SPANSION [SPANSION]

8.4
26
Synchronous (Burst) Read Mode and Configuration Register
banks was in the middle of either a program or erase operation when RESET# was asserted, the user must
wait a period of t
Asserting RESET# during a program or erase operation leaves erroneous data stored in the address
locations being operated on at the time of device reset. These locations need updating after the reset
operation is complete. See
Asserting RESET# active during V
until V
When a series of adjacent addresses need to be read from the device, the synchronous (or burst read) mode
can be used to significantly reduce the overall time needed for the device to output array data. After an initial
access time required for the data from the first address location, subsequent data is output synchronized to a
clock input provided by the system.
The device offers a linear method of burst read operation which is discussed in
Burst Operation on page
Since the device defaults to asynchronous read mode after power-up or a hardware reset, the configuration
register must be set in order to enable the burst read mode. Other Configuration Register settings include the
number of wait states to insert before the initial word (t
that data is ready to be read. Prior to entering the burst mode, the system first determines the configuration
register settings (and read the current register settings if desired via the Read Configuration Register
command sequence), then write the configuration register command sequence. See
on page
burst mode operation, all subsequent reads from the array are returned using the burst mode protocols.
The device outputs the initial word subject to the following operational conditions:
 t
 Configuration register setting CR13-CR10: The total number of clock cycles (wait states) that occur before
Like the main memory access, the Secured Silicon Sector memory is accessed with the same burst or
asynchronous timing as defined in the Configuration Register. However, the user must recognize burst
operations past the 256 byte Secured Silicon boundary returns invalid data.
data on the device outputs.
valid data appears on the device outputs. The effect is that t
IACC
CC
specification: The time from the rising edge of the first clock cycle after addresses are latched to valid
29, and
and V
IO
READY
Table 20.1 on page 75
have reached their steady state voltages. See
before accessing that bank.
27.
Figure 8.2 Synchronous/Asynchronous State Diagram
Hardware Reset (RESET#) on page 62
S29CD-J and S29CL-J Flash Family
Configuration Register
Synchronous Mode
Set Burst Mode
CC
Command for
(D15 = 0)
and V
for further details. Once the configuration register is written to enable
IO
D a t a
Asynchronous Read
Synchronous Read
power-up is required to guarantee proper device initialization
Hardware Reset
Mode Only
Mode Only
Power-up/
IACC
S h e e t
Configuration Register
) of each burst access and when RDY indicates
Asynchronous Mode
Set Burst Mode
IACC
Command for
V
(D15 = 1)
CC
is lengthened.
for timing specifications.
and V
S29CD-J_CL-J_00_B7 October 11, 2012
IO
Power-up on page
2-, 4-, 8- Double Word Linear
Configuration Register
57.