S29CD-J_12 SPANSION [SPANSION], S29CD-J_12 Datasheet - Page 67

• Manufacturer Part Number: S29CD-J_12
• Manufacturer: SPANSION [SPANSION]

Note
The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an erase-suspended sector.
Notes
1. The timings are similar to synchronous read timings and asynchronous data polling Timings/Toggle bit Timing.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the toggle bits will stop toggling.
3. RDY is active with data (A18 = 0 in the Configuration Register). When A18 = 1 in the Configuration Register, RDY is active one clock cycle before data.
4. Data polling requires burst access time delay.
October 11, 2012 S29CD-J_CL-J_00_B7
Addresses
ADV#
Data
OE#
RDY
CE#
CLK
WE#
DQ6
DQ2
Enter Embedded
Erasing
V A
Figure 18.14 Synchronous Data Polling Timing/Toggle Bit Timings
Erase
Figure 18.13 DQ2 vs. DQ6 for Erase/Erase Suspend Operations
Suspend
Erase
t
OE
D a t a
Erase Suspend
S29CD-J and S29CL-J Flash Family
Read
S h e e t
Status Data
Suspend Program
Enter Erase
Erase Suspend
Program
V A
Erase Suspend
Read
t
OE
Resume
Erase
Erase
Status Data
Complete
Erase
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