PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 104

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

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When SENSE INTERRUPT is not Necessary
Interrupts that occur during most command operations do
not need to be identified by the SENSE INTERRUPT. The
microprocessor can identify them by checking the Request
for Master (RQM) bit (bit 7) of the Main Status Register
(MSR). See page “Bit 7 - Request for Master (RQM)” on
page 75.
It is not necessary to issue a SENSE INTERRUPT com-
mand to detect the following causes of Interrupts:
Interrupts caused by these conditions are cleared automat-
ically, or by reading or writing information from or to the
Data Register (FIFO).
Command Phase
Execution Phase
Status of interrupt is reported.
Result Phase
When bit 2 of the second command phase byte (ETR) in the
MODE command is set to 1, the track number is stored as
a 12-bit value. See “Bit 0 - Extended Track Range (ETR)”
on page 92.
In this case, a third result byte should be read to hold the
Most Significant Nibble (MSN), i.e., the four most significant
bits, of the number of the current track.
•
•
7
1
0
0
TABLE 5-22. Interrupt Causes Reported by SENSE
Bits of
7
0
The result phase of any of the following commands
started:
— READ DATA, READ DELETED DATA, READ A
— WRITE DATA, WRITE DELETED
— FORMAT TRACK
— SCAN EQUAL, SCAN EQUAL OR LOW, SCAN
— VERIFY
Data is being transferred in non-DMA mode, during the
execution phase of some command.
ST0
6
1
0
1
TRACK, READ ID
EQUAL OR HIGH
5
0 FDC became ready during drive polling mode.
1 SEEK, RELATIVE SEEK or RECALIBRATE
1 SEEK, RELATIVE SEEK or RELCALIBRATE
6
0
SEEK, RELATIVE SEEK or RECALIBRATE
not completed.
terminated normally.
terminated abnormally.
5
0
INTERRUPT
4
0
Interrupt Cause
3
1
2
0
1
0
0
0
104
Otherwise (ETR bit in MODE is 0), this command phase
byte is not required. and, only two result phase bytes should
be read.
First Command Phase Byte,
Result Phase Status Register 0
Second Command Phase Byte,
Present Track Number (PTR)
Fourth Command Phase Byte,
Bits 7-4 - MSN of Track Number
5.7.20 The SET TRACK Command
This command is used to verify (read) or change (write) the
number of the present track.
This command could be useful for recovery from disk track-
ing errors, where the true track number could be read from
the disk using the READ ID command, and used as input to
the SET TRACK command to correct the Present Track
number (PTR) stored internally.
Termination of this command does not generate an inter-
rupt
Command Phase
When bit 2 of the second command phase byte (ETR) in the
MODE command is set to 1, the track number is stored as
a 12-bit value. See “Bit 0 - Extended Track Range (ETR)”
on page 92.
In this case, issue SET TRACK twice - once for the Most
Significant Byte (MSB) of the number of the current track
and once for the Least Significant Byte (LSB).
Otherwise (ETR bit in MODE is 0), issue SET TRACK only
once, with bit 2 (MSB) of the second command phase byte
set to 0.
7
7
0
0
See “Result Phase Status Register 0 (ST0)” on page 81.
The value in this byte is the number of the current track.
If the track number is stored as a 12-bit value, these bits
contain the Most Significant Nibble (MSN), i.e., the four
most significant bits, of the number of the track to seek.
Otherwise (the ETR bit in the MODE command is 0), this
result phase byte is not required.
MSN of PTR
WNR
6
Result Phase Status Register 0 (ST0)
6
0
Byte of Present Track Number (PTR)
Byte of Present Track Number (PTR)
5
5
1
1
4
4
0
1
3
3
0
0
MSB
2
2
0
DS1
1
1
0
DS0
0
0
1