PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 60

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

www.national.com
Predetermined Wake-Up
The second, minute and hour values of the pre-determined
wake-up times are contained in the Seconds Alarm, Min-
utes Alarm and Hours Alarm registers, respectively (index-
es 01h, 03h and 05h of banks 0, 1 and 2). The Day of Week,
Date of Month, Month, Year and Century of the pre-deter-
mined date is held in bank 2, registers indexes 43h-46h and
48h. These eight registers are compared with the corre-
sponding Seconds, Minutes, Hours, Date of Week, Day of
Month, Month and Year in all banks, register indexes 00, 02,
04, 06, 07, 08, 09 and Century register in bank 1, register
index 48h.
Ring Signal Event
An incoming telephone call is an event that may activate a
transfer from the Power-Off state to a Power-On state, in or-
der to deal with the pending incoming voice, fax or modem
communication.
The part can detect a RING pulse falling edge or a RING
pulse train with a frequency of at least 16 Hz, that lasts at
least 0.19 seconds.
During RING pulse train detection, the existence of falling
edges on RING is monitored during time slots of 62.5 msec
(16 Hz cycle time). A RING pulse train detect event occurs
if falling edge(s) of RING were detected in three consecu-
tive time slots, following a time slot in which no falling edge
of RING was detected.
This method of detecting a RING pulse train filters out (does
not detect) a RING pulse train of less then 11 Hz, might de-
tect a RING pulse train of 11 Hz to 16 Hz, and guarantees
detection of a RING pulse train of at least 16 Hz.
RI1,2 Event
High to Low transitions on RI1 or RI2 indicate communica-
tions activity on the UART inputs, and these conditions may
be used as events to “wake-up” the system.
NOTE: The APC can distinguish between two events of the
4.5 APC REGISTERS
The APC registers reside in the APC bank 2 memory. The
RAM Lock register also resides in this bank. See Table 4-4
on page 55.
The APC registers are not affected by system reset. They
are initialized to 0 only when power is applied for the first
time, i.e., application of one of the voltages V
when no previous voltage was present.
same type if a minimum time of 2.5 periods of the 32Khz
clock passed between their arrivals. Thus, if the APC
detects an event, and another event of the same nature
occurs once again in less than 70ms from the previous
event, the APC might not detect the second event,i.e.,
the event will be lost.
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
BAT
or V
CCH
60
4.5.1
Bit 0 - Reserved
Bit 1 - Switch Off Delay Option
Bit 2 - POR Edge or Level Select
Bit 3 - Level POR Clear Command
Bit 4 - Mask ONCTL Activation if Power Fail (MOAP)
Bit 5 - Software Off Command (SOC)
Bit 6 - Fail-safe Timer Reset Command
Bit 7 - Power Failure
7
Reserved.
0 - 4-5 seconds.
1 - 20-21 seconds.
0 - Edge POR.
1 - Level POR. Once POR is asserted, it remains as-
This is a write-only non-sticky bit. Read returns 0.
0 - Ignored.
1 - POR output signal is deactivated.
0 - When power returns, sets the system to the power
1 - While the Power Failure bit (bit 7 of APCR1) is set,
This bit is write-only and non-sticky. Read returns 0.
0 - Ignored.
1 - ONCTL output signal is deactivated.
This bit is write-only and non-sticky. Read returns 0.
0 - Ignored.
1 - Fail-safe timer is stopped and reset.
Set to 1 when RTC/APC switches from V
Cleared to 0 by writing 1 to this bit. Writing 0 to this bit
has no effect.
Power Failure
6
serted until cleared by Level POR Clear Command
(bit 3).
state that existed when power failed.
mask ONCTL activation, except as a result of a
Switch On Event.
APC Control Register 1 (APCR1), Index 40h
FIGURE 4-11. APCR1 Register Bitmap
Fail-safe Timer Reset Command
5
SOC
4
3
MOAP
Level POR Clear Command
2
POR Edge or Level Select
1
Switch Off Delay Option
0
Power-Up
Reset
Required
Reserved
APC Control
CCH
Register 1
Index 40h
(APCR1)
to V
BAT
.