PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 158

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

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Bits 7-4 - Reserved
7.14.3 Link Control Register (LCR) and Bank Select
These registers are the same as the registers at offset 03h
in bank 0.
7.14.4 Reserved Registers, Bank 4, Offsets 04h -07h
These registers are reserved.
7.15 BANK 5 – INFRARED CONTROL REGISTERS
7.15.1 Reserved Registers, Bank 5, Offsets 00h -02h
These registers are reserved.
7.15.2 (LCR/BSR) Register, Bank 5, Offset 03h
These registers are the same as the registers at offset 03h
in bank 0.
7.15.3 Infrared Control Register 2 (IRCR2), Bank 5,
This register controls the basic settings of the infrared modes.
Upon reset, the content of this register is 02h.
05h - 07h
00-02h
Offset
03h
04h
Read/Write 0.
IR_SL1
TABLE 7-21. Sharp-IR or SIR Mode Selection
0
0
1
1
Register (BSR), Bank 4, Offset 03h
Offset 04h
Register
TABLE 7-22. Bank 5 Registers
IRCR2
Name
LCR/
BSR
IR_SL0
0
1
0
1
Link Control Register/
Bank Select Register
Infrared Control Register 2
Reserved
Reserved
UART1 and UART2 (with IR) (Logical Devices 5 and 6)
Selected Mode
UART (Default)
Description
Sharp-IR
Reserved
SIR
158
Bit 0 - Enable Infrared Full Duplex Mode (IR_FDPLX)
Bit 1 - MSR Register Function Select in Infrared Mode
(IRMSSL)
Bits 3,2 -Reserved
Bit 4 - Auxiliary Infrared Input Select (AUX_IRRX)
Bit 5-7 - Reserved
7.15.4 Reserved Registers, Bank 5, Offsets 05h -07h
These registers are reserved.
0
0
7
When set to 1, the infrared receiver is not masked dur-
ing transmission.
This bit selects the behavior of the Modem Status Reg-
ister (MSR) and the Modem Status Interrupt (MS_EV)
when any infrared mode is selected. When a UART
mode is selected, the Modem Status Register and the
Modem Status Interrupt function normally, and this bit is
ignored.
0 - MSR register and modem status interrupt work in
1 - The MSR returns 30h, and the Modem Status Inter-
Read/Write 0.
When set to 1, the infrared signal is received from the
auxiliary input. (Separate input signals may be desired
for different front-end circuits). See Table 7-31 on page
165.
Read/Write 0.
0
6
the IR modes as in the UART mode (Enables ex-
ternal circuitry to perform carrier detection and pro-
vide wake-up events).
rupt is disabled. (Default)
FIGURE 7-32. IRCR2 Register Bitmap
0
5
Reserved
0
4
AUX_IRRX
0
3
0
2
Reserved
1
1
0
IRMSSL
0
Reset
Required
IR_FDPLX
Infrared Control
Offset 04h
Register 2
(IRCR2)
Bank 5,