PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 17

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

DIR
DR1,0
DRATE0
DRQ3-0
DSKCHG
DSR2,1
DSTRB
DTR2,1
ERR
GPIO17-10
Signal/Pin
Name
90
88, 87
84
55-52
99
143, 133
119
144, 134
116
156-149
Number
Pin
Parallel Port
Parallel Port
ISA-Bus
Purpose
UART1,
UART1,
General
Module
UART2
UART2
FDC
FDC
FDC
FDC
Signal/Pin Connection and Description
Group 16
Group 16
Group 20
Group 18
Group 23
Group 17
Group 10
Group #
Group 1
Group 1
Group 3
I/O and
Output
Output
Output
Output
Output
Output
Input
Input
Input
I/O
Direction (FDC) – This output signal determines the direction of the
Floppy Disk Drive (FDD) head movement (active = step in, inactive =
step out) during a seek operation. During reads or writes, DIR is
inactive.
Drive Select 0 and 1 (FDC) – These active low output signals are
the decoded drive select output signals. DR0 and DR1 are controlled
by Digital Output Register (DOR) bits 0 and 1. They are encoded with
information to control four FDDs when bit 7 of the SuperI/O FDC
Configuration register is 1, as described in Section 2.6.1 on page 36.
See MTR0,1 for more information.
Data Rate 0 (FDC) – This output signal reflects the value of bit 0 of
the Configuration Control Register (CCR) or the Data Rate Select
Register (DSR), whichever was written to last. Output from the pin is
totem-pole buffered (6 mA sink, 6 mA source).
DMA Request 0, 1, 2 and 3 – These active high output signals
inform the DMA controller that a data transfer is needed. These DMA
signals can be mapped to the following logical devices: Floppy Disk
Controller (FDC), UART1, UART2 or parallel port.
Disk Change (FDC) – This input signal indicates whether or not the
drive door has been opened. The state of this pin is available from
the Digital Input Register (DIR). This pin can also be configured as
the RGATE data separator diagnostic input signal via the MODE
command. See the MODE command in Section 5.7.7 starting on
page 92.
Data Set Ready – When low, this signal indicates that the data
transfer device, e.g., modem, is ready to establish a communications
link.
The DSR signal is a modem status input signal whose condition the
CPU can test by reading bit 5 (DSR) of the Modem Status Register
(MSR) for the appropriate channel. Bit 5 is the complement of the
DSR signal. Bit 1 (DDSR) of the MSR indicates whether the DSR
input signal has changed state since the previous reading of the
MSR.
Whenever the DDSR bit of the MSR is set, an interrupt is generated
if modem status interrupts are enabled.
Data Strobe (EPP) – This signal is used in EPP mode as a data
strobe. It is active low.
DSTRB is multiplexed with AFD. See Table 6-12 on page 134 for
more information.
Data Terminal Ready – When low, this output signal indicates to the
modem or other data transfer device that the UART1 or UART2 is
ready to establish a communications link.
The DTR signal can be set active low by programming bit 0 (DTR) of
the Modem Control Register (MCR) to high (1).
A Master Reset (MR) deactivates this signal high, and loopback
operation holds this signal inactive.
DTR2 is multiplexed with CFG1 and BOUT2. DTR1 is multiplexed
with BADDR0 and BOUT1.
Error – This input signal is set active low by the printer when it has
detected an error. This pin is internally connected to a nominal 25 K
pull-up resistor.
General Purpose I/O Signals 17-10 – General purpose I/O signals
of I/O Port 1.
GPIO17 is multiplexed with WDO.
17
Function
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