PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 207

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PC87307VUL

Manufacturer Part Number
PC87307VUL
Description
PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
Manufacturer
National Semiconductor
Datasheet
13.3.17 Enhanced Parallel Port 1.7 Timing
t
t
t
t
t
t
t
t
t
t
WW17
WST17
WEST17
WPD17h
HRW17
WPDS17
EPDW17
EPD17h
ZWS17a
ZWS17h
IOCHRDY
Symbol
WR
RD
ZWS
D7-0
WRITE
DSTRB
ASTRB
PD7-0
WAIT
or
a. The design guarantees that WRITE will not change from low to high before DSTRB, or ASTRB, goes from low
b. D7-0 is stable 15 nsec before WR becomes active.
to high.
WRITE Active or Inactive from WR Active or Inactive
DSTRB or ASTRB Active or Inactive from WR or RD Active or Inactive
DSTRB or ASTRB Active after WRITE Becomes Active
PD7-0 Hold after WRITE Becomes Inactive
IOCHRDY Active or Inactive after WAIT Becomes Active or Inactive
PD7-0 Valid after WRITE Becomes Active
PD7-0 Valid Width
PD7-0 Hold after DSTRB or ASTRB Becomes Inactive
ZWS Valid after WR or RD Active
ZWS Hold after WR or RD Inactive
t
t
WEST17
t
ZWS17a
WW17
t
WST17
TABLE 13-53. Enhanced Parallel Port 1.7 Timing Parameters
t
WPDS17
FIGURE 13-24. Enhanced Parallel Port 1.7 Timing
Parameter
t
HRW17
Device Description
t
t
WW17
WST17
t
HRW17
207
t
ZWS17h
t
WPD17h
t
WST17
t
ZWS17a
t
Notes
HRW17
a
b
Min
50
80
t
0
0
0
WST17
t
Valid
EPD17h
t
EPDW17
Valid
Max
45
45
40
15
45
www.national.com
t
ZWS17h
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
Unit

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