PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 159

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

7.16 BANK 6 – INFRARED PHYSICAL LAYER
This Bank of registers controls aspects of the framing and
timing of the infrared modes.
7.16.1 Infrared Control Register 3 (IRCR3), Bank 6,
This Register enables/disables modulation in Sharp-IR
mode.
Upon reset, the content of this register is 20h.
Bit 0-5 - Reserved
Bit 6 - Sharp-IR Modulation Disable (SHMD_DS)
Bit 7 - Sharp-IR Demodulation Disable (SHDM_DS)
7.16.2 Reserved Register, Bank 6, Offset 01h
This register is reserved.
04h - 07h
0
7
Offset
Read/Write 0.
0 - Enables internal 500KHz transmitter modulation.
1 - Disables internal modulation.
0 - Enables internal 500 KHz receiver demodulation.
1 - Disables internal demodulation.
00h
01h
02h
03h
CONFIGURATION REGISTERS
SHDM_DS
0
6
(Default)
(Default)
Offset 00h
FIGURE 7-33. IRCR3 Register Bitmap
SHMD_DS
1
0
5
TABLE 7-23. Bank 6 Register Set
LCR/ BSR
Register
SIR_PW
0
0
4
IRCR3
Name
0
0
3
0
0
2
0
0
1
Reserved
Infrared Control Register 3
SIR Pulse Width Control
0
0
0
Link Control Register/
Reserved
Bank Select Register
Reserved
Reset
Required
UART1 and UART2 (with IR) (Logical Devices 5 and 6)
( 115 Kbps)
Description
Infrared Control
Register 3
Offset 00h
(IRCR3)
Bank 6,
159
7.16.3 SIR Pulse Width Register (SIR_PW), Bank 6,
This register sets the pulse width for transmitted pulses in
SIR operation mode. These setting do not affect the receiv-
er. Upon reset, the content of this register is 00h, which de-
faults to a pulse width of 3/16 of the baud rate.
Bits 3-0 - SIR Pulse Width Register (SPW)
Bits 7-4 - Reserved
7.16.4 Link Control Register (LCR) and Bank Select
These registers are the same as the registers at offset 03h
in Bank 0.
7.16.5 Reserved Registers, Bank 6, Offsets 04h-07h
These registers are reserved.
7.17 BANK 7 – CONSUMER-IR AND OPTICAL
Bank 7 contains the registers that configure Consumer-IR
functions and infrared transceiver controls. See Table 7-24.
0
0
7
Two codes for setting the pulse width are available. All
other values for this field are reserved.
0000 - Pulse width is 3/16 of the bit period. (Default)
1101 - Pulse width is 1.6 sec.
Read/Write 0’s.
Offset
00h
01h
02h
03h
04h
TRANSCEIVER CONFIGURATION REGISTERS
0
0
6
FIGURE 7-34. SIR_PW Register Bitmap
Offset 02h
Register (BSR), Bank 6, Offset 03h
0
0
5
TABLE 7-24. Bank 7 Register Set
LCR/BSR
Register
IRRXDC
IRTXMC
IRCFG1
RCCFG Consumer-IR Configuration Reg-
0
0
Name
4
Reserved
0
3
0
2
Infrared Interface Configuration
Infrared Receiver Demodulator
Infrared Transmitter Modulator
0
1
Link Control Register/
SPW(3-0)
Bank Select Register
0
0
Control Register
Control Register
Reset
Required
Description
Register 1
ister
SIR Pulse Width
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Offset 02h
(SIR_PW)
Register
Bank 6,