PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 163

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

7.17.3 Consumer-IR Configuration Register (RCCFG),
This register control the basic operation of the Consumer-
IR mode. After reset, the content of this register is 00h.
Bits 1,0 - Transmitter Modulator Mode (RC_MMD(1,0))
Bit 2 - Transmitter Subcarrier Frequency Select
(TXHSC)
Bit 3 - Reserved
Bit 4 - Receiver Demodulation Disable (RCDM_DS)
TABLE 7-30. Transmitter Modulation Mode Selection
0
7
Determines how infrared pulses are generated from the
transmitted bit string. (see Table 7-30).
RCCFG
This bit selects the frequency range for the modulation
carrier.
0 - Low frequency: 30-56.9 KHz
1 - High frequency: 400-480 KHz
Read/Write 0.
When this bit is 1, the internal demodulator is disabled.
The internal demodulator, when enabled, performs car-
rier frequency checking and envelope detection.
This bit must be set to 1 (disabled), when the demodu-
lation is performed externally, or when oversampling
mode is selected to determine the carrier frequency.
R_LEN
Bits
0
6
1 0
0 0
0 1
1 0
1 1
Bank 7, Offset 02h
FIGURE 7-37. RCCFG Register Bitmap
T_OV
0
5
0
RXHSC
C_PLS Modulation mode. Pulses are
generated continuously for the entire logic
0 bit time.
8_PLS Modulation Mode. 8 pulses are
generated each time one or more logic 0
bits are transmitted following a logic 1 bit.
6_PLS Modulation Mode. 6 pulses are
generated each time one or more logic 0
bits are transmitted following a logic 1 bit.
Reserved. Result is indeterminate.
4
Consumer-IR
RCDM_DS
0
0
3
Reserved
0
2
TXHSC
0
1
Modulation Mode
RC_MMD1
0
0
Reset
Required
RC_MMD0
UART1 and UART2 (with IR) (Logical Devices 5 and 6)
Configuration Register
Offset 02h
(RCCFG)
Bank 7,
163
Bit 5 - Receiver Carrier Frequency Select (RXHSC)
Bit 6 - Receiver Sampling Mode Select(T_OV)
Bit 7 - Run Length Control (R_LEN)
7.17.4 Link Control/Bank Select Registers (LCR/BSR),
7.17.5 Infrared Interface Configuration Register 1
This register holds the transceiver configuration data for
Sharp-IR and SIR modes. It is also used to directly control
the transceiver operation mode when automatic configura-
tion is not enabled. The four least significant bits are also
used to read the identification data of a Plug and Play infra-
red interface adaptor.
Bit 0 - Transceiver Identification/Control Bit 0 (IRIC0)
0
7
0 - Internal demodulation enabled.
1 - Internal demodulation disabled.
This bit selects the frequency range for the receiver de-
modulator.
0 - Low frequency: 30-56.9 KHz
1 - High frequency: 400-480 KHz
0 - Programmed-T-period sampling.
1 - Oversampling mode.
Enables or disables run length encoding/decoding. The
format of a run length code is:
where, Y is the bit value and XXXXXXX is the number
of bits minus 1 (Selects from 1 to 128 bits).
0 - Run Length Encoding/decoding is disabled.
1 - Run Length Encoding/decoding is enabled.
These registers are the same as the registers at offset
03h in bank 0.
The function of this bit depends on whether the
ID0/IRSL0/IRRX2 pin is programmed as an input or an
output.
If ID0/IRSL0/IRRX2 is programmed as an input
(IRSL0_DS = 0) then:
— Upon read, this bit returns the logic level of the pin
— Data written to this bit position is ignored.
STRV_MS
0
6
YXXXXXXX
(allowing external devices to identify themselves).
FIGURE 7-38. IRCFG1 Register Bitmap
Bank 7, Offset 03h
(IRCFG1), Bank 7, Offset 04h
0
5
0
4
SIRC(2-0)
0
3
IRID3
0
2
0
1
x
0
IRIC(2-0)
Reset
Required
Infrared Configuration
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Offset 04h
Register 1
(IRCFG1)
Bank 7,